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An Improved Squaring Circuit for Binary Numbers

Author(s): Kabiraj Sethi | Rutuparna Panda

Journal: International Journal of Advanced Computer Sciences and Applications
ISSN 2156-5570

Volume: 3;
Issue: 2;
Start page: 111;
Date: 2012;
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Keywords: Vedic mathematics | VLSI | binary multiplication | hardware design | VHDL

In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

Tango Jona
Tangokurs Rapperswil-Jona

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