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Improving Software Performance in the Compute Unified Device Architecture

Author(s): Alexandru PIRJAN

Journal: Informatica Economica Journal
ISSN 1453-1305

Volume: 14;
Issue: 4;
Start page: 30;
Date: 2010;
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Keywords: Compute Unified Device Architecture | Fermi Architecture | Naive Transpose | Coalesced Transpose | Shared Memory Copy | Loop in Kernel | Loop over Kernel

This paper analyzes several aspects regarding the improvement of software performance for applications written in the Compute Unified Device Architecture CUDA). We address an issue of great importance when programming a CUDA application: the Graphics Processing Unit’s (GPU’s) memory management through ranspose ernels. We also benchmark and evaluate the performance for progressively optimizing a transposing matrix application in CUDA. One particular interest was to research how well the optimization techniques, applied to software application written in CUDA, scale to the latest generation of general-purpose graphic processors units (GPGPU), like the Fermi architecture implemented in the GTX480 and the previous architecture implemented in GTX280. Lately, there has been a lot of interest in the literature for this type of optimization analysis, but none of the works so far (to our best knowledge) tried to validate if the optimizations can apply to a GPU from the latest Fermi architecture and how well does the Fermi architecture scale to these software performance improving techniques.
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