Author(s): Yuet Ming Lam
Journal: International Journal of Computer Science & Information Technology
ISSN 0975-4660
Volume: 4;
Issue: 1;
Start page: 127;
Date: 2012;
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Keywords: Hardware/software codesign | heuristic search | multiple neighborhood functions
ABSTRACT
This paper presents a new approach for mapping and scheduling task graphs for heterogeneous hardware/software computing systems using heuristic search. Task mapping and scheduling are vital in hardware/software codesign and previous approaches that treat them separately lead to suboptimal solutions. In this paper, we propose two techniques to enhance the speedup of mapping/scheduling solutions: (1) an integrated technique combining task clustering, mapping, and scheduling, and (2) a multiple neighborhood function strategy. Our approach is demonstrated by case studies involving 40 randomly generated task graphs, as well as six applications. Experimental results show that our proposed approach outperforms a separate approach in terms of speedup by up to 18.3% for a system with a microprocessor, a floating-point digital signal processor, and an FPGA.
Journal: International Journal of Computer Science & Information Technology
ISSN 0975-4660
Volume: 4;
Issue: 1;
Start page: 127;
Date: 2012;
VIEW PDF
DOWNLOAD PDF Original pageKeywords: Hardware/software codesign | heuristic search | multiple neighborhood functions
ABSTRACT
This paper presents a new approach for mapping and scheduling task graphs for heterogeneous hardware/software computing systems using heuristic search. Task mapping and scheduling are vital in hardware/software codesign and previous approaches that treat them separately lead to suboptimal solutions. In this paper, we propose two techniques to enhance the speedup of mapping/scheduling solutions: (1) an integrated technique combining task clustering, mapping, and scheduling, and (2) a multiple neighborhood function strategy. Our approach is demonstrated by case studies involving 40 randomly generated task graphs, as well as six applications. Experimental results show that our proposed approach outperforms a separate approach in terms of speedup by up to 18.3% for a system with a microprocessor, a floating-point digital signal processor, and an FPGA.
