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Low-power Full Adder array-based Multiplier with Domino Logic

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Author(s): M.B. Damle , Dr. S. S. Limaye

Journal: International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
ISSN 2278-1323

Volume: 1;
Issue: 4;
Start page: 006;
Date: 2012;
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ABSTRACT
A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on Wallace tree technique. Clocked architecture results in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. Higher order multipliers like 16x16, 32x32 may also be implemented using 4x4 bit multiplier and hence a modular design is presented by constructing an 8x8 multiplier using multiple 4x4 multipliers. Average power and TannerTool report for 8x8 Multiplier is as follows, Device and node counts: MOSFETs – 2572, MOSFET geometries - 2 Measurement result summary Average Power found to be 0.11108 microwatt
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