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Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso Platform

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Author(s): Karthik Reddy. G

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 4;
Issue: 4;
Start page: 55;
Date: 2013;
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Keywords: leakage power | GDI | Pass transistor logic | tri-state inverters.

ABSTRACT
Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nanometer technology regime, leakage power has become a major component of total power. Full adder is thebasic functional unit of an ALU. The power consumption of a processor is lowered by lowering the powerconsumption of an ALU, and the power consumption of an ALU can be lowered by lowering the powerconsumption of Full adder. So the full adder designs with low power characteristics are becoming morepopular these days. This proposed work illustrates the design of the low-power less transistor full adderdesigns using cadence tool and virtuoso platform, the entire simulations have been done on 180nm singlen-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V andfrequency of 100MHz. These circuits consume less power with maximum (6T design)of 93.1% power savingcompare to conventional 28T design and 80.2% power saving compare to SERF design without much delaydegradation. The proposed circuit exploits the advantage of GDI technique and pass transistor logic.
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