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Low Power Coding Approach With Error Free Coding Scheme in VLSI Design

Author(s): Rajyalakshmi | SK Rahil Hussain

Journal: International Journal of Engineering Trends and Technology
ISSN 2231-5381

Volume: 5;
Issue: 6;
Start page: 287;
Date: 2013;
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Keywords: power optimization | bit transition | lagger algorithm | hamming code | bus shu ffling | bit streams.

The low power has emerged as a principle design requirement in today’selectronics industry. The need for low power consumption has become important consideration as performance & area. Even several methods exists, still there requires enhancement for optimization of powerconsumption in VLSI circuits. There were several approaches in circuit level, but a very few approaches made at system level, such as bus transition power consumption. A large amount of power gets dissipated under the transition of bit sequence from ‘0’ to ‘1’or ‘1’ to ‘0’ transitions. These powers could be saved if these transitions could be minimized. The power optimization approach in bus transitions using Hamming-coding scheme called ‘Lagger algorithm’ for transition power reduction in VLSI design is to be developed. As to minimize the transition, the code bit streams are shuffledbefore transmission using an Encoder unit and bit streams are regenerated using a decoder algorithm by bus shuffling scheme.The proposed work is to be developed on VHDL definition using active HDL tool for its functional simulation and to be synthesized on Xilinx ISE for synthesis and FPGA editor for its practical realization.
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