Author(s): C. N.Marimuthu | P. Thangaraj | Aswathy Ramesan
Journal: International Journal of Computer Science & Information Technology
ISSN 0975-4660
Volume: 2;
Issue: 3;
Start page: 12;
Date: 2010;
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Keywords: Low power multiplier | low power ring counter | sources of switching activities
ABSTRACT
Today every circuit has to face the power consumption issue for both portable device aiming at largebattery life and high end circuits avoiding cooling packages and reliability issues that are too complex. Itis generally accepted that during logic synthesis power tracks well with area. This means that a largerdesign will generally consume more power. The multiplier is an important kernel of digital signalprocessors. Because of the circuit complexity, the power consumption and area are the two importantdesign considerations of the multiplier. In this paper a low power low area architecture for the shift andadd multiplier is proposed. For getting the low power low area architecture, the modifications made tothe conventional architecture consist of the reduction in switching activities of the major blocks of themultiplier, which includes the reduction in switching activity of the adder and counter. This architectureavoids the shifting of the multiplier register. The simulation result for 8 bit multipliers shows that theproposed low power architecture lowers the total power consumption by 35.25% and area by 52.72 %when compared to the conventional architecture. Also the reduction in power consumption increases withthe increase in bit width.
Journal: International Journal of Computer Science & Information Technology
ISSN 0975-4660
Volume: 2;
Issue: 3;
Start page: 12;
Date: 2010;
VIEW PDF
DOWNLOAD PDF Original pageKeywords: Low power multiplier | low power ring counter | sources of switching activities
ABSTRACT
Today every circuit has to face the power consumption issue for both portable device aiming at largebattery life and high end circuits avoiding cooling packages and reliability issues that are too complex. Itis generally accepted that during logic synthesis power tracks well with area. This means that a largerdesign will generally consume more power. The multiplier is an important kernel of digital signalprocessors. Because of the circuit complexity, the power consumption and area are the two importantdesign considerations of the multiplier. In this paper a low power low area architecture for the shift andadd multiplier is proposed. For getting the low power low area architecture, the modifications made tothe conventional architecture consist of the reduction in switching activities of the major blocks of themultiplier, which includes the reduction in switching activity of the adder and counter. This architectureavoids the shifting of the multiplier register. The simulation result for 8 bit multipliers shows that theproposed low power architecture lowers the total power consumption by 35.25% and area by 52.72 %when compared to the conventional architecture. Also the reduction in power consumption increases withthe increase in bit width.
