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Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data

Author(s): Sunita M.S | Kanchana Bhaaskaran V.S

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 4;
Issue: 1;
Start page: 29;
Date: 2013;
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Keywords: Memory testing | Error correction codes | Matrix code s | multiple error detection | multiple error correct io

Constant shrinkage in the device dimensions has resulted in very dense memory cells. The probability ofoccurrence of multiple bit errors is much higher invery dense memory cells. Conventional ErrorCorrecting Codes (ECC) cannot correct multiple errors in memories even though many of these arecapable of detecting multiple errors. This paper presents a novel decoding algorithm to detect and correctmultiple errors in memory based on Matrix Codes. The algorithm used is such that it can correct amaximum of eleven errors in a 32-bit data and a maximum of nine errors in a 16-bit data. The proposedmethod can be used to improve the memory yield in presence of multiple-bit upsets. It can be applied forcorrecting burst errors wherein, a continuous sequence of data bits are affected when high energeticparticles from external radiation strike memory, and cause soft errors. The proposed technique performsbetter than the previously known technique of errordetection and correction using Matrix Codes.
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