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Network-on-Chip: A New SoC Communication Infrastructure Paradigm

Author(s): Naveen Choudhary

Journal: International Journal of Soft Computing & Engineering
ISSN 2231-2307

Volume: 1;
Issue: 6;
Start page: 332;
Date: 2012;
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Keywords: NoC. SoC | Topology | Routing | Buffers | Virtual Channel.

As the feature size in deep-submicron domain is continuously shrinking and the bandwidth requirements is increasing, traditional shared-bus architecture will no longer be able to meet the requirements of System-on-Chip (SoC) implementations. Specially, inherently non-scalable nature of the shared-bus architecture as well as its power hungry nature will become the communication bottleneck in most practical applications. Network-on-Chip (NoC) communication architectures have emerged as a promising alternative to address the problems associated with on-chip buses by employing a packet-based micro-network for inter-IP communication. Some of the most important phases in designing the NoC are the design of the topology or structure of the network and setting of various design parameters (such as frequency of operation, link-width, etc). This paper surveys the various topological structures for NoC proposed in the research domain
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