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A New Efficient-Silicon Area MDAC Synapse

Author(s): Zied Gafsi | Nejib Hassen | Mongia Mhiri | Kamel Besbes

Journal: American Journal of Applied Sciences
ISSN 1546-9239

Volume: 4;
Issue: 6;
Start page: 378;
Date: 2007;
Original page

Keywords: MDAC | binary representation | efficient silicon area

Using the binary representation in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named Arithmetic MDAC (AMDAC) is designed. It functions with a new representation based on arithmetic progressions. Using the AMS CMOS 0.35┬Ám technology the silicon area is reduced by a factor of 40%.

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