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A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units

Author(s): Ashwini Suresh Deshmukh

Journal: International Journal of Reconfigurable and Embedded Systems (IJRES)
ISSN 2089-4864

Volume: 1;
Issue: 1;
Start page: 19;
Date: 2012;
Original page

In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction.
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