Academic Journals Database
Disseminating quality controlled scientific knowledge

OPTIMIZATION OF LOW POWER USING FIR FILTER

ADD TO MY LIST
 
Author(s): S. Prem Kumar | S. Sivaprakasam, | G. Damodharan, | V. Ellappan

Journal: International Journal on Computer Science and Engineering
ISSN 0975-3397

Volume: 3;
Issue: 6;
Start page: 2290;
Date: 2011;
VIEW PDF   PDF DOWNLOAD PDF   Download PDF Original page

Keywords: FIR | hybrid Multipler and Booth Multiplier

ABSTRACT
In this paper we proposed a three stage pipelined finite-impulse response (FIR) filter, this FIR filter contains multipliers such as Hybrid multiplier, Booth multiplier algorithm and Array multiplier. In general, multiplication process consists of two parts as multiplicand and multiplier. According to the array multiplier, the numbers of partial products (PP) are equal to the number of bits in multiplier. Booth multiplier is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Booth's algorithm can be reduced by half using booth recoding. But in the hybrid multiplication technique, the partial products can still be reduced which in turn reduces the switching activity and power consumption. Multiplication is a very important operation in many digital signal processing (DSP) applications. In our proposed system, the performance of our hybrid multiplier is compared with an array multiplier and booth multiplier. The comparison is based on synthesis results obtained by synthesizing the multiplier architectures targeting a Xilinx FPGA.
Save time & money - Smart Internet Solutions     

Tango Jona
Tangokurs Rapperswil-Jona