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Performance Evaluation on the Basis of Energy in NoCs

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Author(s): Lalit Kishore Arora | Rajkumar

Journal: International Journal of Innovative Technology and Creative Engineering
ISSN 2045-869X

Volume: 1;
Issue: 2;
Start page: 6;
Date: 2011;
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Keywords: Network-on-Chip | Interconnection Networks | Topologies | Multi-core processor.

ABSTRACT
The classical interconnection network topologies such as point-to-point and bus-based, recently has been replaced by the new approach Network-on-Chip (NoC). NoC can consume significant portions of a chip’s energy budget, so analyzing their energy consumption early in the design cycle becomes important for architectural design decisions. Although numerous studies have examined NoC implementation and performance, few have examined energy. This paper determines the energy efficiency of some of the basic network topologies of NoC. We compared them, and results show that the CMesh topology consumes less energy than Mesh topology.
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