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Power Optimized Memory Organization Using Multi - Bit - Flip - Flop Approach and Enhanced Ring Counter

Author(s): kiran Kumar.G | M .Venkata Rao

Journal: International Journal of Engineering Trends and Technology
ISSN 2231-5381

Volume: 5;
Issue: 7;
Start page: 377;
Date: 2013;
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Keywords: Multi - bit - flip - flop | C - elements | Ring counter | clock gating | Merging

Power reduction has become a vital design goal for sophisticateddesign applications, whether mobile or not. dropping power consumption in design enables better, cheaper products to be designed and power-related chip failures to be minimized. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-flop method is to eliminate total inverter number by sharing the inverters in the flip-flops. In this paper, we will review multi-bit flip-flopconcepts, and introduce the benefits of using multi-bit flip-flops in our design. Then, we will show how to implement multi-bit flip-flop methodology by XILINX Design Compiler. Experimental results indicate that multi-bit flip-flop is very effective and efficient method in lower-power designs

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