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Profiling on Superscalar Pipelining Architecture and Multi-Pipeline Scheduling Policies

Author(s): Tarun Bhalla | Mohit Mittal

Journal: International Journal of Computer & Electronics Research
ISSN 2320-9348

Volume: 1;
Issue: 3;
Start page: 88;
Date: 2012;
Original page

Keywords: superscalar pipeline design | pipeline stalling | multipipeline scheduling i.e. in-order issue & in-order completion | in-order issue & out-order completion and out-order issue & out-order completion

In this paper, we present the process of pipelining using superscalar processor. A super-scalar processor is one that is capable of sustaining an instruction-execution rate of more than one instruction per clock cycle. Maintaining this execution rate is primarily a problem of scheduling processor resources (such as functional units) for high utilization. Multiple pipes are used for improving the performance of pipelining. A superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.
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