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Radix-4 Encoder & PPG Block for Multiplier Architecture using GDI Technique

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Author(s): Ankita Dhankar, Satyajit Anand

Journal: International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
ISSN 2278-1323

Volume: 2;
Issue: 3;
Start page: 1192;
Date: 2013;
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Keywords: encoder | multiplier | gate-diffusion input (GDI) | power consumption | PPG

ABSTRACT
A radix-4 encoder & partial product generatorcircuit is implemented that demand high speed and lowenergy operation. It is a good approach if we implement themultiplier as a hybrid architecture of the radix-4/-8 becausethe radix-8 mode has low power consumption capability,occupying less area and number of partial products obtainedin this mode are less(N/3). But the detection of the 3B termwhile computing the partial products is very difficult and itis difficult to implement it on the FPGA board. So bycomparing the performances of the two multipliers wesuggest to go with the radix-4 multiplier. Compared to aconventional CMOS radix-4 encoder & PPG, the proposedcircuit consumes 2.23% less power, 17.51% less averagedelay time with the use of only 74 transistors in comparisonto conventional CMOS circuit which uses 204 transistors.
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