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Reduction of Bus Transition for Compressed Code Systems

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Author(s): S. R. Malathi | R. Ramya Asmi

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 4;
Issue: 1;
Start page: 123;
Date: 2013;
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Keywords: Low power VLSI | Bus transition reduction | Arithmeti c coding | Compressed Code systems.

ABSTRACT
Low power VLSI circuit design is one of the most important issues in present day technology. One of theways of reducing power is to reduce the number of transitions on the bus. The main focus here is to presenta method for reducing the power consumption of compressed-code systems by inverting the bits that aretransmitted on the bus. Compression will generallyincrease bit-toggling, as it removes redundancies fromthe code transmitted on the bus. Arithmetic codingtechnique is used for compression /decompression andbit-toggling reduction is done by using shift invert coding technique. Therefore, there is also an additionalchallenge, to find the right balance between compression ratio and the bit-toggling reduction. Thistechnique requires only 2 extra bits for the low Power coding, irrespective of the bit-width of the bus forcompressed data
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