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A Simple Design to Mitigate Problems of Conventional Digital Phase Locked Loop

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Author(s): M. Saber | Y. Jitsumatsu | M. T. A. Khan

Journal: Signal Processing : An International Journal
ISSN 1985-2339

Volume: 6;
Issue: 2;
Start page: 65;
Date: 2012;
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Keywords: Digital Phase-Locked Loop (DPLL) | Field Programmable Gate Array (FPGA).

ABSTRACT
This paper presents a method which can estimate frequency, phase and power of received signalcorrupted with additive white Gaussian noise (AWGN) in large frequency offset environment.Proposed method consists of two loops, each loop is similar to a phase–locked loop (PLL)structure. The proposed structure solves the problems of conventional PLL such as limitedestimation range, long settling time, overshoot, high frequency ripples and instability. Traditionalinability of PLL to synchronize signals with large frequency offset is also removed in this method.Furthermore, proposed architecture along with providing stability, ensures fast tracking of anychanges in input frequency. Proposed method is also implemented using field programmablegate array (FPGA), it consumes 201 mW and works at 197 MHz.

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