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A Study of 3D IC’s Integration and Formation using TSV

Author(s): Hitesh Joshi, Rajeev Mathur

Journal: International Journal of Engineering Trends and Technology
ISSN 2231-5381

Volume: 3;
Issue: 3;
Start page: 353;
Date: 2012;
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Keywords: VLSI | 3D IC | TSV | GeOI | SoC

In today’s era the demand of Very Large Scale Integrated Circuit (VLSI) is increase due to the growth of the Electronics industry. VLSI has high performance and high functionality at minimum cost and power dissipation. Continuously scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnects delays. The higher power consummation is due to long wiring networks and clock distribution also by the interconnect delays. 3D IC is typically designed by multiple design teams, in multiple geographies, using a variety of design tools. This paper discusses the design of a 3D IC by the formation of integrated circuit; Through-silicon-vias (TSV) based integration modeling techniques, challenges of 3D IC’s integration & packaging and future aspect of 3D IC.
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