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A Survey of Metastability Errors in CMOS Digital Circuits

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Author(s): Manisha Thakur, Puran Gaur, Braj Bihari soni

Journal: International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
ISSN 2278-1323

Volume: 2;
Issue: 1;
Start page: 033;
Date: 2013;
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Keywords: CMOS | metastability | setup & hold time | synchronization.

ABSTRACT
Recent advances in complementary metal oxidesemiconductor (CMOS) technology have led to unparalleledlevels of integration in digital logic systems. By and large, thesedigital logic systems require a clock to synchronize signals andensure proper operation. Due to the path propagation delay andclock synchronization setup hold time failure errors are occursin digital circuits. Depending upon the application, the errorsare described by a number of different terms including“synchronization failure,” “arbitration error,” and“metastability error.” The underlying mechanism for all ofthese problems is the same, and of these terms, “metastabilityerror” is the most general because it describes the failure of theelement within the circuit and not the application. Metastabilityis a widespread phenomenon and errors may occur in anysynchronous circuit where an input signal can change randomlywith respect to a reference signal. The reference signal may beeither a voltage based reference, such as a bias voltage, or a timebased reference, such as a clock signal.
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