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Theory, Analysis and Implementation of an On-LineBIST Technique

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Author(s): Rajiv Sharma | Kewal K. Saluja

Journal: VLSI Design
ISSN 1065-514X

Volume: 1;
Issue: 1;
Start page: 9;
Date: 1993;
Original page

Keywords: Concurrent testing | Test latency | Built-In self test | VLSI Testing | Transient faults | Intermittent faults.
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