Author(s): Minaei Shahram | Yuce Erkan
Journal: IETE Journal of Research
ISSN 0377-2063
Volume: 56;
Issue: 6;
Start page: 305;
Date: 2010;
Original page
Keywords: All-pass filter | CMOS | Current-mode | Dual-X second-generation current conveyor | Variable gain | Voltage-mode
ABSTRACT
In this paper, two new general topologies for realizing voltage-mode (VM)/current-mode (CM) first-order all-pass filter transfer functions (TFs) are presented. The proposed topologies use single dual-X second-generation current conveyor (DXCCII) and three impedances Z1 , Z2 and Z3 . Based on the selection of Z1 , Z2 and Z3 , new VM and CM all-pass filters with unity or variable gains are obtained. The proposed VM/CM filters have high-input/high-output impedances which provide easy cascading at their input/output terminals, respectively. Non-ideal gain and parasitic impedance effects, associated with actual DXCCII implementation, on the performance of the developed topologies are also included. Finally, simulation program with integrated circuit emphasis (SPICE) simulation results based on level 49, 0.25 μm TSMC complementary metal-oxide-semiconductor (CMOS) technology parameters are given to confirm the theory.
Journal: IETE Journal of Research
ISSN 0377-2063
Volume: 56;
Issue: 6;
Start page: 305;
Date: 2010;
Original page
Keywords: All-pass filter | CMOS | Current-mode | Dual-X second-generation current conveyor | Variable gain | Voltage-mode
ABSTRACT
In this paper, two new general topologies for realizing voltage-mode (VM)/current-mode (CM) first-order all-pass filter transfer functions (TFs) are presented. The proposed topologies use single dual-X second-generation current conveyor (DXCCII) and three impedances Z1 , Z2 and Z3 . Based on the selection of Z1 , Z2 and Z3 , new VM and CM all-pass filters with unity or variable gains are obtained. The proposed VM/CM filters have high-input/high-output impedances which provide easy cascading at their input/output terminals, respectively. Non-ideal gain and parasitic impedance effects, associated with actual DXCCII implementation, on the performance of the developed topologies are also included. Finally, simulation program with integrated circuit emphasis (SPICE) simulation results based on level 49, 0.25 μm TSMC complementary metal-oxide-semiconductor (CMOS) technology parameters are given to confirm the theory.
