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Various Flash Memory Devices of Novel Design

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Author(s): Yun Jang-Gn | Lee Jong | Park Byung-Gook

Journal: IETE Technical Review
ISSN 0256-4602

Volume: 26;
Issue: 4;
Start page: 247;
Date: 2009;
Original page

Keywords: Double-recessed channel | Extended word-line | Fin flash memory with separated double-gate structure | Lifted-charge-trapping node scheme | Stacked array | Stacked vertical channel | Word-line double-patterning process.

ABSTRACT
Various novel flash memory devices for both NOR and NAND types are reviewed. In NOR-type flash memory devices, 2-bit/cell devices and their technology trends are addressed. Furthermore, multi-site -charge-trapping schemes with more-than-2-bit/cell operation are also studied in the fin SONOS (silicon oxide-nitride oxide semiconductor) flash memory having independent double gates and the stacked vertical-channel NOR flash memory. In the NAND-type flash memory, devices having extended word-lines are investigated. As well as the short-channel effect, fluctuation and process limitation issues are considered for the highly scaled devices. Some future perspectives, including a stacked array, are discussed for high-density NAND flash memories.
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