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Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

Author(s): Uwe Meyer-Bäse | Hariharan Natarajan | Andrew G. Dempster
Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

Author(s): Mohsen Machhout | Zied Guitouni | Kholdoun Torki | Lazhar Khriji | Rached Tourki
AUTOMATION OF CONVEYOR BELT TRANSPORT

Author(s): Nenad Marinović | Neven Katunarić | Igor Zorić
Implementation of CT and IHT Processors for Invariant Object Recognition System

Author(s): J. Turan | L. Ovsenik | M. Benca | J. Turan jr.
Implementation of a Mobile Accessible Remote Lab

Author(s): Michael E. Auer | A. Y. Al-Zoubi | Danilo Garbi Zutin
Flexible Hardware-Based Stereo Matching

Author(s): Kristian Ambrosch | Wilfried Kubinger | Martin Humenberger | Andreas Steininger
Mechanosensor Channels in Mammalian Somatosensory Neurons

Author(s): Matthieu Raoux | Lise Rodat-Despoix | Nathalie Azorin | Aurélie Giamarchi | Jizhe Hao | François Maingret | Marcel Crest | Bertrand Coste | Patrick Delmas
Neuromorphic Configurable Architecture for Robust Motion Estimation

Author(s): Guillermo Botella | Manuel Rodríguez | Antonio García | Eduardo Ros
AHB Compatible DDR SDRAM Controller IP Core for ARM BASED SOC

Author(s): Dr. R. Shashikumar, | C. N. Vijay Kumar, | M. Nagendrakumar, | C. S. Hemanthkumar,
A Mixed-Signal Embedded Platform for Automotive Sensor Conditioning

Author(s): Emilio Volpi | Luca Fanucci | Adolfo Giambastiani | Alessandro Rocchi | Francesco D'Ascoli | Marco Tonarelli | Massimiliano Melani | Corrado Marino
Simulation and Emulation of MIMO Wireless Baseband Transceivers

Author(s): Pierre Greisen | Simon Haene | Andreas Burg
A Generic Graph-Oriented Mapping Strategy for a Honeycomb Topology

Author(s): Gaurav Kumar Singh | Mythri Alle | Keshavan Vardarajan | S K Nandy | Ranjani Narayan
Optimisation Of VCD Format And Test bench Reuse In Implementation Of ASIC Tester

Author(s): Wani Prakash W | Mehta Rakesh | Talware Rajendra S | Patil Ganesh C
New Class of Cryptographic Primitives and Cipher Design for Networks Security

Author(s): Nikolay Moldovyan | A. A. Moldovyan | M. A. Eremeev | N. Sklavos
A 16-electrode Fully Integrated and Versatile CMOS Microstimulator Dedicated to Cochlear Implant

Author(s): Mohamed Ghorbel | Mounir Samet | Ahmed Ben Hamida | Jean Tomas
High Degree of Testability Using Full Scan Chain and ATPG-An Industrial Perspective

Author(s): Mamun B.I. Reaz | Weng F. Lee | Nor H. Hamid | Hai H. Lo | Ali Y.M. Shakaff
Efficient Implementation of Sample Rate Converter

Author(s): Charanjit singh | Manjeet Singh patterh | Sanjay Sharma
Amiloride Enhances Neuronal Excitability of CA1 Pyramidal Neurons in The Anesthetized Rat

Author(s): Yildirim SARA | Mert ERTUNC | Ozlem BOZDAGI | Rustu ONUR
Antinociception produced by Thalassia testudinum extract BM-21 is mediated by the inhibition of acid sensing ionic channels by the phenolic compound thalassiolin B

Author(s): Garateix Anoland | Salceda Emilio | Menéndez Roberto | Regalado Erik | López Omar | García Teidy | Morales Ruth | Laguna Abilio | Thomas Olivier | Soto Enrique
Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

Author(s): T. Mahnke | W. Stechele | M. Embacher | W. Hoeld
Design of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS Technology

Author(s): Siva Kumar Palaniappan and Tun Zainal Azni Zulkifli
A Systematic Approach to Design Low-Power Video Codec Cores

Author(s): Kristof Denolf | Adrian Chirila-Rus | Paul Schumacher | Robert Turney | Kees Vissers | Diederik Verkest | Henk Corporaal
Efficient Implementation of Nested-Loop Multimedia Algorithms

Author(s): Yu Hen Hu | Surin Kittitornkun
READ - Remote Analog ASIC Design System

Author(s): Danilo G. Zutin | Michael E. Auer
MODELLING AND REAL-TIME SIMULATION OF A NETWORKED-CONTROL SYSTEM WITH DISTRIBUTED LOADS

Author(s): Isizoh A. N. | Inyiama H. C. | Ezeagwu C. O. | Nwokoye A.O. C
Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

Author(s): Frank Volf | Lech Jóźwiak | Mario Stevens
Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

Author(s): B. Majumdar | V. V. Ramakrishna | P. S. Dey | A. K. Majumdar
Estudio comparativo de los divisores en tecnologías CMOS nanométricas

Author(s): Gashaw Sassaw | Carlos J. Jiménez | José M. Mora | Manuel Valencia
VLIW BASED VEX TOOL AND VALIDATION OF SIM-A WITH VEX

Author(s): Dr. Manoj Kumar Jain | Gajendra Kumar Ranka
FPGA Based Secure System Design-an Overview

Author(s): Gurjit Singh Walia | Gajraj Kuldeep | Rajiv Kapoor | A K Sharma | Navneet Gaba
High Performance DCT Implementation using NEDA on FPGA

Author(s): Monika Zope | P. S. Mahajani
A Systematic Approach to Design Low-Power Video Codec Cores

Author(s): Denolf Kristof | Chirila-Rus Adrian | Schumacher Paul | Turney Robert | Vissers Kees | Verkest Diederik | Corporaal Henk
Efficient Implementation of Nested-Loop Multimedia Algorithms

Author(s): Kittitornkun Surin | Hu YuHen
Simulation and Emulation of MIMO Wireless Baseband Transceivers

Author(s): Greisen Pierre | Haene Simon | Burg Andreas
Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

Author(s): Meyer-Bäse Uwe | Natarajan Hariharan | Dempster Andrew G
Flexible Hardware-Based Stereo Matching

Author(s): Ambrosch Kristian | Kubinger Wilfried | Humenberger Martin | Steininger Andreas
A Mixed-Signal Embedded Platform for Automotive Sensor Conditioning

Author(s): Volpi Emilio | Fanucci Luca | Giambastiani Adolfo | Rocchi Alessandro | D'Ascoli Francesco | Tonarelli Marco | Melani Massimiliano | Marino Corrado
LOW NOISE LOW POWER READOUT CIRCUIT FOR SOFT X RAY DETECTION

Author(s): A. Cerdeira-Estrada | A. De Luca | A. Cuttin | R. Mutihac
Operator Design Methodology and Application in H.264 Entropy Coding

Author(s): Ziyi Hu | Teng Wang | Kuilin Chen | Zheng Xie | Xin'an Wang
A SMART CAMERA PROCESSING PIPELINE FOR IMAGE APPLICATIONS UTILIZING MARCHING PIXELS

Author(s): Michael Schmidt | Marc Reichenbach | Andreas Loos | Dietmar Fey
Area Efficient Design of Routing Node for Network-on-Chip

Author(s): Rehan Maroofi | Vilas Nitnaware | Shyam Limaye
Efficient DPA Attacks on AES Hardware Implementations

Author(s): Yu HAN | Xuecheng ZOU | Zhenglin LIU | Yicheng CHEN
Comparative study of Braun’s Multiplier Using FPGA Devices

Author(s): Anitha R, | Bagyaveereswaran V
VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

Author(s): Rozita Teymourzadeh | Yazan S. Algnabi | Masuri Othman | Md S. Islam | Jimmy M.V. Hong
Digital Hardware Implementation of a Neural System Used for Nonlinear Adaptive Prediction

Author(s): Hassène Faiedh | Chokri Souani | Kholdoun Torki | Kamel Besbes
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