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Search Articles for "Digital Multiplier; Optimization; Urdhva Tiryakbhayam; Vertical and crosswise algorithm"

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Single electron based binary multipliers with overflow detection

Author(s): Souvik Sarkar | Anup Kumar Biswas | Ankush Ghosh | Subir Kumar Sarkar
HIGH SPEED BUTTERFLY ARCHITECTURE FOR CIRCULAR CONVOLUTION USING FNT WITH PARTIAL PRODUCT MULTIPLIER

Author(s): HEMALATHA BANDARI | ALAHARI RADHIKA, | SAKE POTHALAIAH | Dr.K ASHOK BABU
Comparison of reconfigurable structures for flexible word-length multiplication

Author(s): O. A. Pfänder | R. Nopper | H.-J. Pfleiderer | S. Zhou | A. Bermak
High Speed Vedic Multiplier for Digital Signal Processors

Author(s): Pushpangadan Ramesh | Sukumaran Vineeth | Innocent Rino | Sasikumar Dinesh | Sundar Vaisak
Two-Dimensional Digital Filters with Variable Magnitude Characteristics Obtained from a 1-D Monotonic Response

Author(s): Venkat Ramachandran | Christian S. Gargour | Ravi P. Ramachandran
LOW POWER SHIFT AND ADD MULTIPLIER DESIGN

Author(s): C. N.Marimuthu | P. Thangaraj | Aswathy Ramesan
Low Cost Quantum Realization of Reversible Multiplier Circuit

Author(s): M.S. Islam | M.M. Rahman | Z. Begum | M.Z. Hafiz
A Bit-Serial Multiplier Architecture for Finite Fields Over Galois Fields

Author(s): Hero Modares | Yasser Salem | Rosli Salleh | Majid T. Shahgoli
VLSI IMPLEMENTATION OF AN ANALOG MULTIPLIER FOR MODEM

Author(s): SRIVIDYA .P, | KR REKHA | Dr. K.R NATARAJ
Configurable multiplier modules for an adaptive computing system

Author(s): O. A. Pfänder | H.-J. Pfleiderer | S. W. Lachowicz
Low-Power Embedded DSP Core for Communication Systems

Author(s): Shyh-Jye Jou | Maw-Ching Lin | Ming Hsuan Tan | Wei-Hao Chen | Ya-Lan Tsao
A New Efficient-Silicon Area MDAC Synapse

Author(s): Zied Gafsi | Nejib Hassen | Mongia Mhiri | Kamel Besbes
FPGA Based Hardware Efficient Digital Decimation Filter for Σ-Δ ADC

Author(s): Subir Kr. Maity | Himadri Sekhar Das
LOW POWER NOVEL HYBRID ADDERS FOR DATAPATH CIRCUITS IN DSP PROCESSOR

Author(s): B. Sathiyabama | Dr. S. Malarkkan
Performance Evaluation and Synthesis of Vedic Multiplier

Author(s): Umesh Akare | T. V. More | R. S. Lonkar
Low Power Multiplier Design Using Latches and Flip-Flops

Author(s): C. N. Marimuthu | P. Thangaraj
Symbolic sensitivity analysis of the new second–order IIR structure

Author(s): G. Jovanovic–Dolecek | S.K. Mitra
Performance evaluation of high speed compressors for high speed multipliers

Author(s): Nirlakalla Ravi | Subba Rao Thota | Jayachandra-Prasad Talari
Low-Power Embedded DSP Core for Communication Systems

Author(s): Tsao Ya-Lan | Chen Wei-Hao | Tan Ming Hsuan | Lin Maw-Ching | Jou Shyh-Jye
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

Author(s): Hoare Raymond R | Jones Alex K | Kusic Dara | Fazekas Joshua | Foster John | Tung Shenchih | McCloud Michael
High speed multiplier design using Decomposition Logic

Author(s): Ramanathan Palaniappan | Vanathi Thangapandian Ponnisamy | Agarwal Sundeepkumar
An Improved Wavelet Filtering Algorithm and Its FPGA Implementation

Author(s): Lan Yang | Xiang-mo Zhao | Fei Hui | Xin Shi
Guest Editorial

Author(s): Mohamed Masmoudi
Parallel MAC Based On Radix-4 & Radix-8 Booth Encodings

Author(s): SHANKEY GOEL | R.K. SHARMA
OPTIMIZATION OF LOW POWER USING FIR FILTER

Author(s): S. Prem Kumar | S. Sivaprakasam, | G. Damodharan, | V. Ellappan
A HIGHLY TIME-EFFICIENT DIGITAL MULTIPLIER BASED ON THE A2 BINARY REPRESENTATION

Author(s): Hatem BOUKADIDA, | Nejib HASSEN, | Zied GAFSI, | Kamel BESBES
Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers

Author(s): Muhammad H. Rais | Bandar M. Al-Harthi | Saad I. Al-Askar | Fahad K. Al-Hussein

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