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Design and VLSI implementation of Fuzzy Logic Controller

Author(s): Balwinder Singh , Rajneesh Goyal , Rakesh Kumar and R.P.P Singh
High-Performance Timing-Driven Rank Filter

Author(s): Péter Szántó | Gábor Szedő | Béla Fehér
FPGA-based Low Power Audio Subword Sorter Unit

Author(s): Karthigaikumar P | Baskaran K
Optimization of Chip Interconnect Area by using Interconnect Length and Width

Author(s): D.Venkata Vara Prasad | Dr.Y.Venkatarami Reddy
Serial ALU Simulation with Timing and Signal Constraints

Author(s): Muhammad Kamran | Shi Feng | Sana Qureshi
Seguridad en redes. Diseño e implementación de un cifrador de datos por medio de DES triple

Author(s): Ana Maria López Echeverry | Diego Fernando Rojas Rincón
Quantitative design space exploration of routing-switches for Network-on-Chip

Author(s): M. C. Neuenhahn | H. Blume | T. G. Noll
Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

Author(s): JunKyu Lee | Gregory D. Peterson | Robert J. Harrison | Robert J. Hinde
A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Author(s): Akila Gothandaraman | Gregory D. Peterson | G. Lee Warren | Robert J. Hinde | Robert J. Harrison
VLSI Architecture of a Cellular Automata based One-Way Function

Author(s): D. Mukhopadhyay | P. Joshi | D. RoyChowdhury
New Class of Cryptographic Primitives and Cipher Design for Networks Security

Author(s): Nikolay Moldovyan | A. A. Moldovyan | M. A. Eremeev | N. Sklavos
A Novel design of High Speed Adders Using Quaternary Signed Digit Number System

Author(s): Reena Rani, L.K. Singh and Neelam Sharma
High Speed and Low Space Complexity FPGA Based ECC Processor

Author(s): Rahila Bilal | Dr.M.Rajaram
Efficient Implementation of Sample Rate Converter

Author(s): Charanjit singh | Manjeet Singh patterh | Sanjay Sharma
Design Approach for Fault Tolerance in FPGA Architecture

Author(s): Ms. Shweta S. Meshram | Ujwala A. Belorkar
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

Author(s): Alberto Jiménez-Pacheco | Ángel Fernández-Herrero | Javier Casajús-Quirós
Enabling VLSI Processing Blocks for MIMO-OFDM Communications

Author(s): Barbara Cerato | Guido Masera | Emanuele Viterbo
An FPGA-Based Electronic Cochlea

Author(s): Philip H. W. Leong | Craig T. Jin | M. P. Leong
Technology Mapping for FPGA Using GeneralizedFunctional Decomposition

Author(s): Kuo-Hua Wang | Cheng Chen | Ting Ting Hwang
Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

Author(s): Frank Volf | Lech Jóźwiak | Mario Stevens
A Sea-of-Gates Style FPGA Placement Algorithm

Author(s): Kalapi Roy | Bingzhong (David) Guan | Carl Sechen
A Timing-Driven Partitioning System for Multiple FPGAs

Author(s): Kalapi Roy | Carl Sechen
DP-FPGA: An FPGA Architecture Optimized for Datapaths

Author(s): Don Cherepacha | David Lewis
FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC

Author(s): Bolla Leela Naresh | N.V.Narayana Rao | Addanki Purna Ramesh
IMPLEMENTATION OF KARATSUBA ALGORITHM USING POLYNOMIAL MULTIPLICATION

Author(s): SUDHANSHU MISHRA | MANORANJAN PRADHAN
Fast FPGA Implementation of EBCOT block in JPEG2000 Standard

Author(s): Anass Mansouri | Ali Ahaitouf | Farid Abdi
An FPGA-Based Electronic Cochlea

Author(s): Leong MP | Jin Craig T | Leong Philip HW
FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System

Author(s): Ho Quoc-Thai | Massicotte Daniel | Dahmane Adel-Omar
Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis

Author(s): Ivanović Veselin N | Stojanović Radovan | Stanković L Jubivša
An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

Author(s): Ginhac Dominique | Dubois Jérôme | Paindavoine Michel | Heyrman Barthélémy
AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

Author(s): P. Tirumala rao | P. Siva kumar | Y.V. Apparao | Y. Madhu babu
FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision

Author(s): Guillermo Botella | José Antonio Martín H. | Matilde Santos | Uwe Meyer-Baese
Dynamic Partial Reconfiguration of FPGA for SEU Mitigation and Area Efficiency

Author(s): Vijay G Savani | Akash I Mecwan | Nagendra P Gajjar
VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Author(s): Rondia MACK | Maher RIZKALLA | Paul SALAMA | Mohamed EL-SHARKAWY
An Asynchronous Multi-Sensor Micro Control Unit for Wireless Body Sensor Networks (WBSNs)

Author(s): Chiung-An Chen | Shih-Lun Chen | Hong-Yi Huang | Ching-Hsing Luo
Efficient Fuzzy C-Means Architecture for Image Segmentation

Author(s): Hui-Ya Li | Wen-Jyi Hwang | Chia-Yen Chang
FPGA IMPLEMENTATION OF IP PROTECTION THROUGH VISUAL INFORMATION HIDING

Author(s): ABHISHEK BASU, | DEBAPRIYA BASU ROY, | DEEP BANERJEE, | ARCHAN SENGUPTA, | ANIKET SAHA, | TIRTHA SANKAR DAS, | S.K. SARKAR
Computerised Speech Processing in Hearing Aids using FPGA Architecture

Author(s): V. Hanuman Kumar | Prof. P. Seetha Ramaiah
VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

Author(s): Rozita Teymourzadeh | Yazan S. Algnabi | Masuri Othman | Md S. Islam | Jimmy M.V. Hong

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