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A Video Specific Instruction Set Architecture for ASIP design

Author(s): Zheng Shen | Hu He | Yanjun Zhang | Yihe Sun
High-Performance Timing-Driven Rank Filter

Author(s): Péter Szántó | Gábor Szedő | Béla Fehér
CORDIC Architectures: A Survey

Author(s): B. Lakshmi | A. S. Dhar
Fault Detection Multipliers in Polynomial and Normal Basis

Author(s): Siddharth Shelly | Babu T Chacko
A Novel Coarse-to-fine Search Motion Estimator

Author(s): Reeba Korah | J. Raja Paul Perinbam
A Novel Low Power and High Performance 14 Transistor CMOS Full Adder Cell

Author(s): T. Vigneswaran | B. Mukundhan | P. Subbarami Reddy
Advanced Readout System IC Current Mode Semi-Gaussian Shapers Using CCIIs and OTAs

Author(s): Thomas Noulis | Constantinos Deradonis | Stylianos Siskos
Area and Power Modeling for Networks-on-Chip with Layout Awareness

Author(s): Paolo Meloni | Igor Loi | Federico Angiolini | Salvatore Carta | Massimo Barbaro | Luigi Raffo | Luca Benini
Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

Author(s): Andreas Hansson | Kees Goossens | Andrei Rădulescu
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Author(s): Srinivasan Murali | David Atienza | Luca Benini | Giovanni De Micheli
Enabling VLSI Processing Blocks for MIMO-OFDM Communications

Author(s): Barbara Cerato | Guido Masera | Emanuele Viterbo
Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System

Author(s): Somayeh Timarchi | Omid Kavehei | Keivan Navi
Integrated VCOs for Medical Implant Transceivers

Author(s): Ahmet Tekin | Mehmet R. Yuce | Wentai Liu
Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Author(s): Pierangelo Terreni | Luca Fanucci | Sergio Saponara
Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

Author(s): Giacomo Mario Bisio | Paolo Cavalleri | Fabio Solari | Silvio P. Sabatini
Design of Area and Power Efficient Modified Carry Select Adder

Author(s): Sarabdeep Singh | Dilip Kumar
Fast Signed-Digit Multi-operand Decimal Adders

Author(s): Jeff Rebacz | Erdal Oruklu | Jafar Saniie
Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Author(s): Saponara Sergio | Fanucci Luca | Terreni Pierangelo
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

Author(s): Guo Yuanbin | Zhang Jianzhong(Charlie) | McCain Dennis | Cavallaro Joseph R
POWER EFFICIENT DESIGN OF COUNTER ON .12 MICRON TECHNOLOGY

Author(s): Simmy Hirkaney | Sandip Nemade | Vikash Gupta
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