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FPGA BASED FIR FILTER

Author(s): SUVARNA JOSHI, | BHARATI AINAPURE
Design of COFDM Transceiver Using VHDL

Author(s): Hemant Kumar Sharma | Sanjay P. Sood | Balwinder Singh
IMPLEMENTATION OF DIGITAL QPSK MODULATOR BY USING VHDL / MATLAB

Author(s): Teena Sakla, | Divya Jain | Sandhya Gautam
A Chaotic IP Watermarking in Physical Layout Level Based on FPGA

Author(s): W. Liang | X. Sun | Z. Xia | D. Sun | J. Long
Hardware Co-simulation For Video Processing Using Xilinx System Generator

Author(s): T. Saidani | D. Dia | W. Elhamzi | M. Atri | R. Tourki
Power Optimized Programmable Embedded Controller

Author(s): M.Kamaraju | K.Lalkishore | A.V.N.Tilak
FPGA Implementation of Daubeshies Polyphase-Decimator filter

Author(s): Abdelhakim SAHOUR | Mohamed Benouaret
High Speed and Low Space Complexity FPGA Based ECC Processor

Author(s): Rahila Bilal | Dr.M.Rajaram
Power Optimized ALU for Efficient Datapath

Author(s): M.Kamaraju | K.Lal Kishore | A.V.N.Tilak
Novel and Efficient Cellular Automata Based Symmetric Key Encryption Algorithm for Wireless Sensor Networks

Author(s): K.J. Jegadish Kumar | K. Chenna Kesava Reddy | S. Salivahanan
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves

Author(s): Sameh M. Shohdy | Ashraf B. El-Sisi | Nabil Ismail
Reconfigurable Hardware Intelligent Memory Controller for H.264/AVC Encoders

Author(s): Kamel Messaoudi | El-Bay Bourennane | Salah Toumi
Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

Author(s): Ignacio Bravo | Javier Baliñas | Alfredo Gardel | José L. Lázaro | Felipe Espinosa | Jorge García
Efficient Hardware Design and Implementation of AES Cryptosystem

Author(s): Pravin B. Ghewari | Mrs. Jaymala K. Patil | Amit B. Chougule
Design and Implementation of High Performance AHB Arbiter for on chip Bus Architecture

Author(s): ASHUTOSH KUMAR SINGH, | VIMLESH SAHU, | KUSH SONI, | RITA JAIN
Performance Evaluation of Squaring Operation by Vedic Mathematics

Author(s): Kasliwal Prabha | Patil B | Gautam D
FPGA IMPLEMENTATION OF MAC HEADER BLOCK OF TRANSMITTER FOR Wi-Fi

Author(s): A.M.BHAVIKATTI, | HAMEEDMIYAN, | DHIRAJ DESHPANDE, | L.M.DESHPANDE
FPGA IMPLEMENTATION OF MAC HEADER BLOCK OF TRANSMITTER FOR Wi-Fi

Author(s): A.M.BHAVIKATTI, | HAMEEDMIYAN, | DHIRAJ DESHPANDE, | L.M.DESHPANDE
On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM

Author(s): Rozita Teymourzadeh | Yazan S. Algnabi | Nooshin Mahdavi | Masuri B. Othman
Application of FPGA's in Flexible Analogue Electronic Image Generator Design

Author(s): Peter Kulla | Stefan Slavik | Josef Huska
Verilog-Based Design and Implementation of Digital Transmitter for Zigbee Applications

Author(s): Rafidah Ahmad | Othman Sidek | Hafizi Wan Hassin | Shukri Korakkottil Kunhi Mohd | Abdullah Sanusi Husain
FPGA Implementation for Real-Time Background Subtraction Based on Horprasert Model

Author(s): Rafael Rodriguez-Gomez | Enrique J. Fernandez-Sanchez | Javier Diaz | Eduardo Ros
Implementation Analysis of adaptive Viterbi Decoder for High Speed Applications

Author(s): P. Subhashini | D. R. Mahesh Varma | Y. David Solomon Raju
Síntesis y evaluación de un DSP empotrado en una FPGA

Author(s): Raidel Herrera Pereda | Juan Raúl Rodríguez Suárez
Diseño de un módulo IP para controlar dispositivos DDS utilizando un núcleo de interfaz PCI

Author(s): Nelia Rosa León González | Abdel Martínez Alonso
Controlador empotrado en FPGA para Sistema Inteligente de Transporte

Author(s): Alejandro Cabrera Aldaya | Alejandro José Cabrera Sarmiento
Diseño de bloques de convolución para procesado de imágenes con FPGA

Author(s): Luis Manuel Garcés Socarrás | Alejandro José Cabrera Sarmiento | Santiago Sánchez Solano | Piedad Brox Jiménez
FPGA Based Hardware Efficient Digital Decimation Filter for Σ-Δ ADC

Author(s): Subir Kr. Maity | Himadri Sekhar Das
Implementation of Back Propagation Algorithm in Verilog

Author(s): Neelmani Chhedaiya | Prof. Vishal Moyal
MODULACIÓN DE SEÑALES BINARIAS POR POSICIÓN DE PULSO EN DISPOSITIVOS FPGA

Author(s): DORA MAR A BALLESTEROS | PAULINE GAMMA | WILLINGTON CAMACHO
Application of FPGA's in Flexible Analogue Electronic Image Generator Design

Author(s): Peter Kulla | Stefan Slavik | Josef Huska
Used in Image Acquisition Area CCD Driving Circuit Design

Author(s): Yan Yan Liu | Guo ning Li
Efficient Hand off using Fuzzy and Simulated Annealing

Author(s): Vikas.M.N | Keshava.K.N | Prabhas.R.K | Hameem Shanavas.I
Computational Modeling of Cell Survival Using VHDL

Author(s): Shruti Jain1, | Pradeep K. Naik | Sunil V. Bhooshan
A Novel Architecture of I2C Slave using One-Hot Encoding Technique

Author(s): Devashree Mahato | Sulipta Das | Durga Prasad Dash
Implementation of Binary Multiplication using Booth and Systolic Algorithm on FPGA using VHDL

Author(s): Jayashree Taralabenchi | Kavana Hegde | Soumya Hegde | Siddalingesh S. Navalgund
Channelization and Frequency Tuning using FPGA for UMTS Baseband Application

Author(s): Mahesh M.Gadag | S. Ganesh Naik | Vinayak Miskin | Dundesh S. K
Hardware Implementation of Mix Column Step in AES

Author(s): Pratap Kumar Dakua | Manoranjan Pradhan | Subba Rao Polamuri
Reliability Increasing Method Using a SEC-DED Hsiao Code to Cache Memories, Implemented with FPGA Circuits

Author(s): NOVAC Ovidiu | SZTRIK Janos | VARI-KAKAS Stefan | KIM Che-Soong
A SystemC-Based Design Methodology for Digital Signal Processing Systems

Author(s): Haubelt Christian | Falk Joachim | Keinert Joachim | Schlichter Thomas | Streubühr Martin | Deyhle Andreas | Hadert Andreas | Teich Jürgen
Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs

Author(s): Sen Mainak | Corretjer Ivan | Haim Fiorella | Saha Sankalita | Schlessman Jason | Lv Tiehan | Bhattacharyya ShuvraS | Wolf Wayne
Adaptive Motion Estimation Processor for Autonomous Video Devices

Author(s): Dias T | Momcilovic S | Roma N | Sousa L
A High-End Real-Time Digital Film Processing Reconfigurable Platform

Author(s): Heithecker Sven | do Carmo Lucas Amilcar | Ernst Rolf
FPGA Dynamic Power Minimization through Placement and Routing Constraints

Author(s): Wang Li | French Matthew | Davoodi Azadeh | Agarwal Deepak
Prototyping Advanced Control Systems on FPGA

Author(s): Simard Stéphane | Mailloux Jean-Gabriel | Beguenane Rachid
OV-CDMA System: Concept and Implementation

Author(s): Inaty Elie | Ayoubi Rafic
Generic Hardware Architectures for Sampling and Resampling in Particle Filters

Author(s): Athalye Akshay | Bolić Miodrag | Hong Sangjin | Djurić Petar M
FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System

Author(s): Ho Quoc-Thai | Massicotte Daniel | Dahmane Adel-Omar
VLSI Implementation of Adders for High Speed ALU

Author(s): Prashant Gurjar | Rashmi Solanki | Pooja Kansliwal | Mahendra Vucha
IMPLEMENTATION OF A NEURON MODEL USING FPGAS

Author(s): M. A. Bañuelos-Saucedo | J. Castillo-Hernández | S. Quintana-Thierry | R. Damián-Zamacona | J. Valeriano-Assem | R. E. Cervantes | R. Fuentes-González | G. Calva-Olmos | J. L. Pérez-Silva
FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

Author(s): Vikram Arkalgud Chandrasetty | Syed Mahfuzul Aziz
Configuration scheme for small scale Multi-FPGA systems

Author(s): Chengchang Zhang | Lisheng Yang | Dangui Yan | Changyong Li
Guest Editorial

Author(s): Syed Mahfuzul Aziz | Vijayan K. Asari | M. Alamgir Hossain | Mohammad Ataul Karim | Mariofanna Milanova
Fast Algorithm of A 64-bit Decimal Logarithmic Converter

Author(s): Ramin Tajallipour | Md. Ashraful Islam | Khan Wahid
An Quadrant-XYZ routing algorithm for 3-D Asymmetric Torus Network-on-Chip

Author(s): Mohammad Ayoub Khan | Abdul Quaiyum Ansari Ansari
Low Power Address Generator for Memory Built-In Self Test

Author(s): Ahmed N. Awad | Abdallatif S.Abu-Issa
A 16-Bit Fully Functional Single Cycle Processor

Author(s): Nidhi Maheshwari | Pramod Kumar Jain | D.S. Ajnar
Design and Hardware Implementation of QoSS - AES Processor for Multimedia applications

Author(s): Zeghid Medien | Mohsen Machhout | Belgacem Bouallegue | Lazhar Khriji | Adel Baganne | Rached Tourki
A Novel Architecture for Motion Estimation

Author(s): Subarna Chatterjee
FPGA Based Design and Implementation of Efficient Video Filter

Author(s): Rajesh Mehra | Virendra Arya | Rajpati Yadav
Architectural Analysis of RSA Cryptosystem on FPGA

Author(s): Vibhor Garg | V. Arunachalam
Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm

Author(s): Narendra Singh Pal | Harjit Pal Singh | R.K. Sarin | Sarabjeet Singh
Frame Detection For Synchronization In OFDM

Author(s): Rakhi Thakur | Kavita Khare
VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Author(s): Rondia MACK | Maher RIZKALLA | Paul SALAMA | Mohamed EL-SHARKAWY
Real Time Image Segmentation using watershed algorithm on FPGA

Author(s): BHUPINDER VERMA, | Dr. H.K.SARDANA
Analysis of WavePipelined Architecture of ARALDPC Codes

Author(s): M. Anbuselvi | S.Salivahanan | P. Saravanan
Comparative study of Braun’s Multiplier Using FPGA Devices

Author(s): Anitha R, | Bagyaveereswaran V
OPTIMAL SELF CORRECTING FAULT FREE ERROR CODING TECHNIQUE IN MEMORY OPERATION

Author(s): Harikishore .Kakarla | Madhavi Latha .M | Habibulla Khan
OPTIMIZATION OF LOW POWER USING FIR FILTER

Author(s): S. Prem Kumar | S. Sivaprakasam, | G. Damodharan, | V. Ellappan
High Speed CT Image Reconstruction Using FPGA

Author(s): Payal Aggarwal | Rajesh Mehra
MAC Implementation using Vedic Multiplication Algorithm

Author(s): Manoranjan Pradhan | Rutuparna Panda | Sushanta Kumar Sahu
Computerised Speech Processing in Hearing Aids using FPGA Architecture

Author(s): V. Hanuman Kumar | Prof. P. Seetha Ramaiah
VHDL Modeling, Simulation and Prototyping of a Novel Arbitrary Signal Generation System

Author(s): S. A. Abbasi | A. R.M. Alamoud | J. M.A. Shahrani
VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

Author(s): Rozita Teymourzadeh | Yazan S. Algnabi | Masuri Othman | Md S. Islam | Jimmy M.V. Hong
On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture

Author(s): Yazan S. Algnabi | Rozita Teymourzadeh | Masuri Othman | Md S. Islam | Mok V. Hong
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