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SIMULATIVE INVESTIGATIONS OF DDR2 (SDRAM) MODEL IN HDL

Author(s): Ajay Kumar | V.Sulochana Verma
DESIGN OF LOW POWER PHASE LOCKED LOOP IN SUBMICRON TECHNOLOGY

Author(s): Kanika Garg | V.Sulochana Verma
HDL IMPLEMENTATION OF DATA COMPRESSION: LZW ALGORITHM

Author(s): Simrandeep kaur | V.Sulochana Verma
CROSSTALK NOISE AND DELAY REDUCTION IN VLSI INTERCONNECTS

Author(s): Shikha Singh | V.Sulochana Verma
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