Single electron based binary multipliers with overflow detection
Author(s): Souvik Sarkar | Anup Kumar Biswas | Ankush Ghosh | Subir Kumar Sarkar
Author(s): Souvik Sarkar | Anup Kumar Biswas | Ankush Ghosh | Subir Kumar Sarkar
HIGH SPEED BUTTERFLY ARCHITECTURE FOR CIRCULAR CONVOLUTION USING FNT WITH PARTIAL PRODUCT MULTIPLIER
Author(s): HEMALATHA BANDARI | ALAHARI RADHIKA, | SAKE POTHALAIAH | Dr.K ASHOK BABU
Author(s): HEMALATHA BANDARI | ALAHARI RADHIKA, | SAKE POTHALAIAH | Dr.K ASHOK BABU
Design of Digital FIR Filter Based on Dynamic Distributed Arithmetic Algorithm
Author(s): T. Vigneswaran | P. Subbarami Reddy
Author(s): T. Vigneswaran | P. Subbarami Reddy
Comparison of reconfigurable structures for flexible word-length multiplication
Author(s): O. A. Pfänder | R. Nopper | H.-J. Pfleiderer | S. Zhou | A. Bermak
Author(s): O. A. Pfänder | R. Nopper | H.-J. Pfleiderer | S. Zhou | A. Bermak
Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme
Author(s): S.Saravanan | M.Madheswaran
Author(s): S.Saravanan | M.Madheswaran
High Speed Vedic Multiplier for Digital Signal Processors
Author(s): Pushpangadan Ramesh | Sukumaran Vineeth | Innocent Rino | Sasikumar Dinesh | Sundar Vaisak
Author(s): Pushpangadan Ramesh | Sukumaran Vineeth | Innocent Rino | Sasikumar Dinesh | Sundar Vaisak
Optimization of FRM FIR Digital Filters Over CSD and CDBNS Multiplier Coefficient Spaces Employing a Novel Genetic Algorithm
Author(s): Patrick Mercier | Sai Mohan Kilambi | Behrouz Nowrouzian
Author(s): Patrick Mercier | Sai Mohan Kilambi | Behrouz Nowrouzian
Two-Dimensional Digital Filters with Variable Magnitude Characteristics Obtained from a 1-D Monotonic Response
Author(s): Venkat Ramachandran | Christian S. Gargour | Ravi P. Ramachandran
Author(s): Venkat Ramachandran | Christian S. Gargour | Ravi P. Ramachandran
LOW POWER SHIFT AND ADD MULTIPLIER DESIGN
Author(s): C. N.Marimuthu | P. Thangaraj | Aswathy Ramesan
Author(s): C. N.Marimuthu | P. Thangaraj | Aswathy Ramesan
Low Cost Quantum Realization of Reversible Multiplier Circuit
Author(s): M.S. Islam | M.M. Rahman | Z. Begum | M.Z. Hafiz
Author(s): M.S. Islam | M.M. Rahman | Z. Begum | M.Z. Hafiz
A Bit-Serial Multiplier Architecture for Finite Fields Over Galois Fields
Author(s): Hero Modares | Yasser Salem | Rosli Salleh | Majid T. Shahgoli
Author(s): Hero Modares | Yasser Salem | Rosli Salleh | Majid T. Shahgoli
VLSI IMPLEMENTATION OF AN ANALOG MULTIPLIER FOR MODEM
Author(s): SRIVIDYA .P, | KR REKHA | Dr. K.R NATARAJ
Author(s): SRIVIDYA .P, | KR REKHA | Dr. K.R NATARAJ
Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs
Author(s): A. Flocke | H. Blume | T. G. Noll
Author(s): A. Flocke | H. Blume | T. G. Noll
Configurable multiplier modules for an adaptive computing system
Author(s): O. A. Pfänder | H.-J. Pfleiderer | S. W. Lachowicz
Author(s): O. A. Pfänder | H.-J. Pfleiderer | S. W. Lachowicz
Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs
Author(s): Myung H. Sunwoo | Jaesung Lee | Jung H. Lee
Author(s): Myung H. Sunwoo | Jaesung Lee | Jung H. Lee
Low-Power Embedded DSP Core for Communication Systems
Author(s): Shyh-Jye Jou | Maw-Ching Lin | Ming Hsuan Tan | Wei-Hao Chen | Ya-Lan Tsao
Author(s): Shyh-Jye Jou | Maw-Ching Lin | Ming Hsuan Tan | Wei-Hao Chen | Ya-Lan Tsao
An Overview of Modified Shanks' Conjecture and Comments on its Validity
Author(s): N. Gangatharan | T. C. Chuah
Author(s): N. Gangatharan | T. C. Chuah
A New Efficient-Silicon Area MDAC Synapse
Author(s): Zied Gafsi | Nejib Hassen | Mongia Mhiri | Kamel Besbes
Author(s): Zied Gafsi | Nejib Hassen | Mongia Mhiri | Kamel Besbes
FPGA Based Hardware Efficient Digital Decimation Filter for Σ-Δ ADC
Author(s): Subir Kr. Maity | Himadri Sekhar Das
Author(s): Subir Kr. Maity | Himadri Sekhar Das
LOW POWER NOVEL HYBRID ADDERS FOR DATAPATH CIRCUITS IN DSP PROCESSOR
Author(s): B. Sathiyabama | Dr. S. Malarkkan
Author(s): B. Sathiyabama | Dr. S. Malarkkan
Performance Evaluation and Synthesis of Vedic Multiplier
Author(s): Umesh Akare | T. V. More | R. S. Lonkar
Author(s): Umesh Akare | T. V. More | R. S. Lonkar
Cosine Modulated Non-Uniform Filter Bank with Improved Computational Efficiency
Author(s): Jyotsna v. Ogale | Alok Jain
Author(s): Jyotsna v. Ogale | Alok Jain
Symbolic sensitivity analysis of the new second–order IIR structure
Author(s): G. Jovanovic–Dolecek | S.K. Mitra
Author(s): G. Jovanovic–Dolecek | S.K. Mitra
Performance evaluation of high speed compressors for high speed multipliers
Author(s): Nirlakalla Ravi | Subba Rao Thota | Jayachandra-Prasad Talari
Author(s): Nirlakalla Ravi | Subba Rao Thota | Jayachandra-Prasad Talari
Low-Power Embedded DSP Core for Communication Systems
Author(s): Tsao Ya-Lan | Chen Wei-Hao | Tan Ming Hsuan | Lin Maw-Ching | Jou Shyh-Jye
Author(s): Tsao Ya-Lan | Chen Wei-Hao | Tan Ming Hsuan | Lin Maw-Ching | Jou Shyh-Jye
Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs
Author(s): Lee Jung H | Lee Jaesung | Sunwoo Myung H
Author(s): Lee Jung H | Lee Jaesung | Sunwoo Myung H
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions
Author(s): Hoare Raymond R | Jones Alex K | Kusic Dara | Fazekas Joshua | Foster John | Tung Shenchih | McCloud Michael
Author(s): Hoare Raymond R | Jones Alex K | Kusic Dara | Fazekas Joshua | Foster John | Tung Shenchih | McCloud Michael
High speed multiplier design using Decomposition Logic
Author(s): Ramanathan Palaniappan | Vanathi Thangapandian Ponnisamy | Agarwal Sundeepkumar
Author(s): Ramanathan Palaniappan | Vanathi Thangapandian Ponnisamy | Agarwal Sundeepkumar
An Improved Wavelet Filtering Algorithm and Its FPGA Implementation
Author(s): Lan Yang | Xiang-mo Zhao | Fei Hui | Xin Shi
Author(s): Lan Yang | Xiang-mo Zhao | Fei Hui | Xin Shi
Digital Topology Optimization Design and Manufacturing Based on the Level Set Method
Author(s): Sen Liang | Y.X. Zhang
Author(s): Sen Liang | Y.X. Zhang
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.
Author(s): Anitha R | Bagyaveereswaran V
Author(s): Anitha R | Bagyaveereswaran V
Digital High Order Multiplier-free Delta Sigma Modulator for Multistandard Fractional-N Frequency Synthesizer
Author(s): Manel Ben-Romdhane | Aymen Abeda | Chiheb Rebai
Author(s): Manel Ben-Romdhane | Aymen Abeda | Chiheb Rebai
A Novel Diversity-Controlled Genetic Algorithm for Optimization of BIBO Stable Digital IF Filters Over CSD Multiplier Coefficient Space
Author(s): Yifan Wu | Behrouz Nowrouzian | Syed Bokhari
Author(s): Yifan Wu | Behrouz Nowrouzian | Syed Bokhari
O boom ambiental na imprensa - Uma análise das notícias sobre desmatamentos e queimadas na Amazônia da década de 70 aos anos 2000
Author(s): Luciana Miranda Costa
Author(s): Luciana Miranda Costa
Spartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay Study
Author(s): Mohammed H. Al-Mijalli
Author(s): Mohammed H. Al-Mijalli
A Low-Power CMOS Programmable CNN Cell and its Application to Stability of CNN with Opposite-Sign Templates
Author(s): S. El-Din | A. K. Abol Seoud | A. El-Fahar
Author(s): S. El-Din | A. K. Abol Seoud | A. El-Fahar
OPTIMIZATION OF LOW POWER USING FIR FILTER
Author(s): S. Prem Kumar | S. Sivaprakasam, | G. Damodharan, | V. Ellappan
Author(s): S. Prem Kumar | S. Sivaprakasam, | G. Damodharan, | V. Ellappan
A HIGHLY TIME-EFFICIENT DIGITAL MULTIPLIER BASED ON THE A2 BINARY REPRESENTATION
Author(s): Hatem BOUKADIDA, | Nejib HASSEN, | Zied GAFSI, | Kamel BESBES
Author(s): Hatem BOUKADIDA, | Nejib HASSEN, | Zied GAFSI, | Kamel BESBES
Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices
Author(s): Muhammad H. Rais
Author(s): Muhammad H. Rais
Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers
Author(s): Muhammad H. Rais | Bandar M. Al-Harthi | Saad I. Al-Askar | Fahad K. Al-Hussein
Author(s): Muhammad H. Rais | Bandar M. Al-Harthi | Saad I. Al-Askar | Fahad K. Al-Hussein
Hardware Implementation of a Genetic Algorithm Based Canonical Singed Digit Multiplierless Fast Fourier Transform Processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband Applications
Author(s): Mahmud Benhamid | Masuri B. Othman
Author(s): Mahmud Benhamid | Masuri B. Othman
A Novel Approach for Testing Stability of 1-D Recursive Digital Filters Based on Lagrange Multipliers
Author(s): K. R. Santhi | N. Gangatharan | M. Ponnavaikko
Author(s): K. R. Santhi | N. Gangatharan | M. Ponnavaikko
