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International Journal of VLSI Design & Communication Systems

ISSN: 0976--1527
Publisher: Academy & Industry Research Collaboration Center (AIRCC)


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Synthesis Optimization for Finite State Machine Design in FPGAs PDF available

Author(s): R.Uma | P.Dhavachelvan
Volume: 3
Issue: 6
Year: 2013
Design of Reversible Multipliers for Linear Filtering Applications in DSP PDF available

Author(s): Rakshith Saligram | Rakshith T.R
Volume: 3
Issue: 6
Year: 2013
Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology PDF available

Author(s): Joyashree Bag | Rajanna K M | Subir Kumar Sarkar
Volume: 3
Issue: 6
Year: 2013
Performance Evaluation of Throughput Maximization in MC-CDMA for 4G Standard PDF available

Author(s): Hema Kale | C.G. Dethe | M.M. Mushrif
Volume: 3
Issue: 6
Year: 2013
Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates PDF available

Author(s): H R Bhagyalakshmi | M K Venkatesha
Volume: 3
Issue: 6
Year: 2013
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture PDF available

Author(s): Hanie Ghaedrahmat | Khosrow Hajsadeghi
Volume: 3
Issue: 6
Year: 2013
Low Cost Reversible Signed Comparator PDF available

Author(s): Farah Sharmin | Rashida Hasan | Rajib Kumar Mitra | Anisur Rahman
Volume: 4
Issue: 5
Year: 2013
An Integrated-Approach for Designing and Testing Specific Processors PDF available

Author(s): Cesar Giacomini Penteado | Sérgio Takeo Kofuji | Edward David Moreno
Volume: 4
Issue: 5
Year: 2013
Low Power Reduced Instruction Set Architecture Using Clock Gating Technique PDF available

Author(s): M.Kamaraju | G.Chinavenkateswararao
Volume: 4
Issue: 5
Year: 2013
A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier PDF available

Author(s): Shridhar R. Sahu | A. Y. Deshmukh
Volume: 4
Issue: 5
Year: 2013
Design of Ultra Low Power 8-Channel Analog Multiplexer Using Dynamic Threshold for Biosignals PDF available

Author(s): D.Hari Priya | V. Rajesh | P. Rama Krishna | K. S. Rao
Volume: 4
Issue: 5
Year: 2013
Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI) Technique PDF available

Author(s): Y. Syamala | K. Srilakshmi | N. Somasekhar Varma
Volume: 4
Issue: 5
Year: 2013
Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits PDF available

Author(s): K.Srilakshmi | Y.Syamala | A.Suvir Vikram
Volume: 4
Issue: 5
Year: 2013
A New Improved MCML Logic for DPA Resistant Circuits PDF available

Author(s): A.K.Tripathy | A.Prathiba | V.S.Kanchana Bhaaskaran
Volume: 4
Issue: 5
Year: 2013
Design and Implementation of Complex Floating Point Processor Using FPGA PDF available

Author(s): Murali Krishna Pavuluri | T.S.R. Krishna Prasad | Ch.Rambabu
Volume: 4
Issue: 5
Year: 2013
Modified March C-With Concurrency in Testing for Embedded Memory Applications PDF available

Author(s): Muddapu Parvathi | N.Vasantha | K.Satya Parasad
Volume: 3
Issue: 5
Year: 2012
Quaternary Logic and Applications Using Multiple Quantum Well Based SWSFETs PDF available

Author(s): P. Gogna | M. Lingalugari | J.Chandy | F.Jain | E.Heller | E-S.Hasaneen
Volume: 3
Issue: 5
Year: 2012
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme PDF available

Author(s): Majed ValadBeigi | Farshad Safaei | Bahareh Pourshirazi
Volume: 3
Issue: 5
Year: 2012
Improved Extended XY On-Chip Routing in Diametrical 2D MEsh NOC PDF available

Author(s): Prasun Ghosal | Tuhin Subhra Das
Volume: 3
Issue: 5
Year: 2012
Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System PDF available

Author(s): Chaitali Biswas Dutta | Partha Garai | Amitabha Sinha
Volume: 3
Issue: 5
Year: 2012
Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design PDF available

Author(s): Kiran Agarwal Gupta | Dinesh K Anvekar | Venkateswarlu V
Volume: 3
Issue: 5
Year: 2012
An Efficient Approach for Four-Layer Channel Routing in VLSI Design PDF available

Author(s): Ajoy Kumar Khan | Bhaskar Das | Tapas Kumar Bayen
Volume: 3
Issue: 5
Year: 2012
A XOR Threshold Logic Implementation Through Resonant Tunneling Diode PDF available

Author(s): Nitesh Kumar Dixit | Vinod Kumari
Volume: 3
Issue: 5
Year: 2012
Design & Analysis of A Charge Re-Cycle Based Novel Lphs Adiabatic Logic Circuits for Low Power Applications PDF available

Author(s): Sanjeev Rai | Ram Awadh Mishra | Govind Krishna Pal | Sudarshan Tiwari
Volume: 3
Issue: 5
Year: 2012
High Fin Width Mosfet Using Gaa Structure PDF available

Author(s): S.L.Tripathi | Ramanuj Mishra | R.A.Mishra
Volume: 3
Issue: 5
Year: 2012
Design and Implementation of Analog Multiplier with Improved Linearity PDF available

Author(s): Nandini A.S | Sowmya Madhavan | Chirag Sharma
Volume: 3
Issue: 5
Year: 2012
Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM PDF available

Author(s): Prathima. A | Kiran Bailey | K.S.Gurumurthy
Volume: 3
Issue: 5
Year: 2012
Modeling of Built-In Potential Variations of Cylindrical Surrounding Gate (CSG) MOSFETs PDF available

Author(s): Santosh Kumar Gupta | S.Baishya
Volume: 3
Issue: 5
Year: 2012
Low Power Dynamic Buffer Circuits PDF available

Author(s): Amit Kumar Pandey | Ram Awadh Mishra | Rajendra Kumar Nagaria
Volume: 3
Issue: 5
Year: 2012
Extended K-Map for Minimizing Multiple Output Logic Circuits PDF available

Author(s): Palash Das | Bikromadittya Mondal
Volume: 4
Issue: 4
Year: 2013
Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso Platform PDF available

Author(s): Karthik Reddy. G
Volume: 4
Issue: 4
Year: 2013
A New Low Voltage P-MOS Bulk Driven Current Mirror Circuit PDF available

Author(s): Anuj Dugaya | Laxmi Kumre
Volume: 4
Issue: 4
Year: 2013
Design of High Efficiency Two Stage Power Amplifier in 0.13µM RF CMOS Technology for 2.4GHZ WLAN Application PDF available

Author(s): Shridhar R. Sahu | A.Y. Deshmukh
Volume: 4
Issue: 4
Year: 2013
Performance Analysis of Modified QSERL Circuit PDF available

Author(s): Shipra Upadhyay | R.A. Mishra | R. K. Nagaria
Volume: 4
Issue: 4
Year: 2013
Analog Modeling of Recursive Estimator Design with Filter Design Model PDF available

Author(s): R.Rajendra prasad | M.V.Subramanyam | K.Satya Prasad
Volume: 4
Issue: 4
Year: 2013
Improved Algorithm for Throughput Maximization in MC-CDMA PDF available

Author(s): Hema Kale | C.G. Dethe | M.M. Mushrif
Volume: 3
Issue: 4
Year: 2012
FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme PDF available

Author(s): Durga Sowjanya | K N H Srinivas | P Venkata Ganapathi
Volume: 3
Issue: 4
Year: 2012
Delay Error with Meta - Stability Detection and Correction Using CMOS Transmission Logic PDF available

Author(s): Bhawna Kankane | Sandeep Sharma | Navaid Zafar Rizvi
Volume: 3
Issue: 4
Year: 2012
Design and Implementation A different Architectures of mixcolumn in FPGA PDF available

Author(s): Sliman Arrag | Abdellatif Hamdoun | Abderrahim Tragha | Salah eddine Khamlich
Volume: 3
Issue: 4
Year: 2012
Deadlock Recovery Technique in Bus Enhanced NoC Architecture PDF available

Author(s): Saeid Sharifian Nia | Abbas Vafaei | Hamid Shahimohamadi
Volume: 3
Issue: 4
Year: 2012
Logic Optimization Using Technology Independent MUX Based Adders in FPGA PDF available

Author(s): R.Uma | P.Dhavachelvan
Volume: 3
Issue: 4
Year: 2012
Magnetic Resonance Brain Image Segmentation PDF available

Author(s): M.C.Jobin Christ | R.M.S.Parvathi
Volume: 3
Issue: 4
Year: 2012
Effect of Equal and Mismatched Signal Transition Time on Power Dissipation in Global VLSI Interconnects PDF available

Author(s): Devendra Kumar Sharma | Brajesh Kumar Kaushik | R.K.Sharma
Volume: 3
Issue: 4
Year: 2012
Universal Rotate Invert Bus Encoding for Low Power VLSI PDF available

Author(s): Shankaranarayana Bhat M | D. Yogitha Jahnavi
Volume: 3
Issue: 4
Year: 2012
Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits PDF available

Author(s): Rajani H.P | Srimannarayan Kulkarni
Volume: 3
Issue: 4
Year: 2012
Design of Low Power Sigma Delta ADC PDF available

Author(s): Mohammed Arifuddin Sohel | K. Chenna Kesava Reddy | Syed Abdul Sattar
Volume: 3
Issue: 4
Year: 2012
Shield Insertion to Minimize Noise Amplitude in Global Interconnects PDF available

Author(s): Kalpana.A.B | P.V.Hunagund
Volume: 3
Issue: 4
Year: 2012
A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates PDF available

Author(s): Md. Sazzad Hossain | Md. Rashedul Hasan Rakib | Md. Motiur Rahman | A. S. M. Delowar Hossain | Md. Minul Hasan
Volume: 2
Issue: 4
Year: 2012
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization PDF available

Author(s): Bhavana Pote | V. N. Nitnaware | S. S. Limaye
Volume: 2
Issue: 4
Year: 2012
Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology PDF available

Author(s): Rajendra Prasad S | B K Madhavi | K Lal Kishore
Volume: 2
Issue: 4
Year: 2012
A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs PDF available

Author(s): Ramya Menon C. | Vinod Pangracious
Volume: 2
Issue: 4
Year: 2012
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell PDF available

Author(s): Viplav A. Soliv | Ajay A. Gurjar
Volume: 2
Issue: 4
Year: 2012
Low Power Low Voltage Bulk Driven Balanced OTA PDF available

Author(s): Neha Gupta | Meenakshi Suthar | Sapna Singh | Priyanka Soni
Volume: 2
Issue: 4
Year: 2012
Design and ASIC Implemenatation of DUC/DDC for Communication Systems PDF available

Author(s): Naagesh S. Bhat
Volume: 2
Issue: 4
Year: 2012
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology PDF available

Author(s): Rita M. Shende | Pritesh R. Gumble
Volume: 2
Issue: 4
Year: 2012
A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation PDF available

Author(s): Vasantha Kumar B.V.P | N. S. Murthy Sharma | K. Lal Kishore | Jibanjeet Mishra
Volume: 2
Issue: 4
Year: 2012
Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level PDF available

Author(s): M.S.Suma | K.S.Gurumurthy
Volume: 2
Issue: 4
Year: 2012
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate PDF available

Author(s): Manoj Kumar | Sandeep K. Arya | Sujata Pandey
Volume: 2
Issue: 4
Year: 2012
Design of Reversible Sequential Circuit Using Reversible Logic Synthesis PDF available

Author(s): Md. Belayet Ali | Md. Mosharof Hossin | Md. Eneyat Ullah
Volume: 2
Issue: 4
Year: 2012
FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC PDF available

Author(s): Bolla Leela Naresh | N.V.Narayana Rao | Addanki Purna Ramesh
Volume: 2
Issue: 4
Year: 2012
A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates PDF available

Author(s): Md. Sazzad Hossain | Md. Rashedul Hasan Rakib | Md. Motiur Rahman | A. S. M. Delowar Hossain | Md. Minul Hasan
Volume: 2
Issue: 4
Year: 2
A New Full Adder Cell for Molecular Electronics PDF available

Author(s): Mehdi Ghasemi | Mohammad Hossein Moaiyeri | Keivan Navi
Volume: 2
Issue: 4
Year: 2012
Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory PDF available

Author(s): Subashri T | Arunachalam R | Gokul Vinoth Kumar B | Vaidehi V
Volume: 1
Issue: 4
Year: 2010
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low Power applications PDF available

Author(s): Shanthala S | Cyril Prasanna Raj P | S.Y.Kulkarni
Volume: 1
Issue: 4
Year: 2010
Single Electron Transistor: Applications & Problems PDF available

Author(s): Om Kumar | Manjit Kaur
Volume: 1
Issue: 4
Year: 2010
An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System Generator PDF available

Author(s): S. Allin Christe | M.Vignesh | A.Kandaswamy
Volume: 2
Issue: 4
Year: 2012
A Review of the 0.09 uM Standard Full Adders PDF available

Author(s): V. Vijay | J. Prathiba | S. Niranjan Reddy | P. Praveen kumar
Volume: 3
Issue: 3
Year: 2012
Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog PDF available

Author(s): Addanki Purna Ramesh | A.V. N. Tilak | A.M.Prasad
Volume: 3
Issue: 3
Year: 2012
Design and Performance Analysis of Ultra Low Power 6T SRAM Using Adiabatic Technique PDF available

Author(s): Sunil Jadav | Vikrant | Munish Vashisath
Volume: 3
Issue: 3
Year: 2012
Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate (PPPG) PDF available

Author(s): Krishna Murthy M | Gayatri G | Manoj Kumar R
Volume: 3
Issue: 3
Year: 2012
Performance Evaluation of CDMA Router for Network-On-Chip PDF available

Author(s): Anant W. Hinganikar | Mahendra A. Gaikwad | Rajendra M. Patrikar
Volume: 3
Issue: 3
Year: 2012
Design and Performance Analysis of Nine Stages CMOS Based Ring Oscillator PDF available

Author(s): Sushil Kumar | Gurjit Kaur
Volume: 3
Issue: 3
Year: 2012
A High Efficiency Charge Pump for Low Voltage Devices PDF available

Author(s): Aamna Anil | Ravi Kumar Sharma
Volume: 3
Issue: 3
Year: 2012
A Novel Full Adder Cell Based on Carbon Nanotube Field Effect Transistors PDF available

Author(s): Ali Ghorbani | Mehdi Sarkhosh | Elnaz Fayyazi | Neda Mahmoudi | Peiman Keshavarzian
Volume: 3
Issue: 3
Year: 2012
Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit PDF available

Author(s): Rajkumar Sarma | Veerati Raju
Volume: 3
Issue: 3
Year: 2012
CNFET Based Basic Gates and a Novel FullAdder Cell PDF available

Author(s): Fazel Sharifi | Amir Momeni | keivan Navi
Volume: 3
Issue: 3
Year: 2012
A Comparative Study of Ultra-Low Voltage Digital Circuit Design PDF available

Author(s): Aaron Arthurs | Justin Roark | Jia Di
Volume: 3
Issue: 3
Year: 2012
TEST GENERATION FOR ANALOG AND MIXED-SIGNAL CIRCUITS USING HYBRID SYSTEM MODELS PDF available

Author(s): Tarik NAHHAL | Thao Dang
Volume: 2
Issue: 3
Year: 2011
A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits PDF available

Author(s): Mouna Karmani | Chiraz Khedhiri | Belgacem Hamdi | Brahim Bensalem
Volume: 2
Issue: 3
Year: 2011
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP PDF available

Author(s): Rehan Maroofi | V. N. Nitnaware | S. S. Limaye
Volume: 2
Issue: 3
Year: 2011
PIPELINED ARCHITECTURE OF 2D-DCT, QUANTIZATION AND ZIGZAG PROCESS FOR JPEG IMAGE COMPRESSION USING VHDL PDF available

Author(s): T.Pradeepthi | Addanki Purna Ramesh
Volume: 2
Issue: 3
Year: 2011
SUB TEN MICRON CHANNEL DEVICES ACHIEVED BY VERTICAL ORGANIC THIN FILM TRANSISTOR PDF available

Author(s): Abdul Rauf Khan | S.S.K. Iyer
Volume: 2
Issue: 3
Year: 2011
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITS PDF available

Author(s): Y. Sunil Gavaskar Reddy | V.V.G.S.Rajendra Prasad
Volume: 2
Issue: 3
Year: 2011
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APPLICATIONS PDF available

Author(s): Subhra Dhar | Manisha Pattanaik | P. Rajaram
Volume: 2
Issue: 3
Year: 2011
FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID REGISTER EXCHANGE METHOD

Author(s): R .D. Kadam | S. L. Haridas
Volume: 2
Issue: 3
Year: 2011
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic PDF available

Author(s): P.Prasad Rao | Lal Kishore
Volume: 2
Issue: 3
Year: 2011
MODELLING AND SIMULATION OF 128-BIT CROSSBAR SWITCH FOR NETWORK -ONCHIP PDF available

Author(s): Mohammad Ayoub Khan | Abdul Quaiyum Ansari
Volume: 2
Issue: 3
Year: 2011
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques. PDF available

Author(s): Anitha R | Bagyaveereswaran V
Volume: 2
Issue: 3
Year: 2011
LINEARITY AND ANALOG PERFORMANCE ANALYSIS OF DOUBLE GATE TUNNEL FET: EFFECT OF TEMPERATURE AND GATE STACK PDF available

Author(s): RAKHI NARANG | MANOJ SAXENA | R. S. GUPTA | MRIDULA GUPTA
Volume: 2
Issue: 3
Year: 2011
POWER AWARE PHYSICAL MODEL FOR 3D IC’S PDF available

Author(s): Yasmeen Hasan
Volume: 2
Issue: 3
Year: 2011
SOFTWARE AND HARDWARE DESIGN CHALLENGES IN AUTOMOTIVE EMBEDDED SYSTEM PDF available

Author(s): Rajeshwari Hegde | Geetishree Mishra | K S Gurumurthy
Volume: 2
Issue: 3
Year: 2011
AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES PDF available

Author(s): P. Tirumala rao | P. Siva kumar | Y.V. Apparao | Y. Madhu babu
Volume: 2
Issue: 3
Year: 2011
DESIGN OF A CMOS BANDGAP REFERENCE WITH LOWTEMPERATURE COEFFICIENT AND HIGH POWER SUPPLY REJECTION PERFORMANCE PDF available

Author(s): Abhisek Dey | Tarun Kanti Bhattacharyya
Volume: 2
Issue: 3
Year: 2011
DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD PDF available

Author(s): Priya Gupta | Deepak Gupta
Volume: 2
Issue: 3
Year: 2011
Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA PDF available

Author(s): VEENA M.B | M.N.SHANMUKHA SWAMY
Volume: 2
Issue: 3
Year: 2011
Reducing power in using different technologies using FSM architecture PDF available

Author(s): Himani Mitta | Dinesh Chandra | Sampath Kumar
Volume: 2
Issue: 3
Year: 2011
Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET PDF available

Author(s): Rajni Gautam | Manoj Saxena | R.S.Gupta | Mridula Gupta
Volume: 2
Issue: 3
Year: 2011
Statistical Modelling of ft to Process Parameters in 30 NM Gate Length Finfets PDF available

Author(s): B. Lakshmi | R. Srinivasan
Volume: 1
Issue: 3
Year: 2010
Low Power Reversible Parallel Binary Adder/Subtractor PDF available

Author(s): Rangaraju H G | Venugopal U | Muralidhara K N | Raja K B
Volume: 1
Issue: 3
Year: 2010
Heuristic approach to optimize the number of test cases for simple circuits PDF available

Author(s): SM. Thamarai | K.Kuppusamy | T. Meyyappan
Volume: 1
Issue: 3
Year: 2010
A High-Swing OTA with wide Linearity for design of self-tunable linear resistor PDF available

Author(s): Nikhil Raj | R.K.Sharma
Volume: 1
Issue: 3
Year: 2010
Design of Near-Threshold CMOS Logic Gates PDF available

Author(s): N. Geetha Rani | N. Praveen Kumar | B. Stephen Charles | S.Md.Imran Ali | P. Chandrasekhar Reddy
Volume: 3
Issue: 2
Year: 2012
Threshold Voltage Control Schemes in Finfets PDF available

Author(s): V. Narendar | Ramanuj Mishra | Sanjeev Rai | Nayana R | R. A. Mishra
Volume: 3
Issue: 2
Year: 2012
Design and Noise Optimization of RF Low Noise Amplifier for IEEE Standard 802.11A WLAN PDF available

Author(s): Ravinder Kumar | Viranjay M. Srivastava | Munish Kumar
Volume: 3
Issue: 2
Year: 2012
A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation PDF available

Author(s): Usha Bhanu.N | A.Chilambuchelvan
Volume: 3
Issue: 2
Year: 2012
Fault Secure Encoder and Decoder with Clock Gating PDF available

Author(s): N.Kapileswar | P.Vijaya Santhi
Volume: 3
Issue: 2
Year: 2012
An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications PDF available

Author(s): P.Rajeswari | A.R.Ashwatha | R.Ramesh
Volume: 3
Issue: 2
Year: 2012
Wishbone Bus Architecture - A Survey and Comparison PDF available

Author(s): Mohandeep Sharma | Dilip Kumar
Volume: 3
Issue: 2
Year: 2012
FPGA Implementation of ADPLL with Ripple Reduction Techniques PDF available

Author(s): Manoj kumar | Kusum Lata
Volume: 3
Issue: 2
Year: 2012
Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders PDF available

Author(s): M.Bharathi | K.Neelima
Volume: 3
Issue: 2
Year: 2012
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology PDF available

Author(s): Ishit Makwana | Vitrag Sheth
Volume: 3
Issue: 2
Year: 2012
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips PDF available

Author(s): P.A.HarshaVardhini | M.Madhavi Latha
Volume: 3
Issue: 2
Year: 2012
Microcontroller Based Testing of Digital IP-Core PDF available

Author(s): Amandeep Singh | Balwinder Singh
Volume: 3
Issue: 2
Year: 2012
Cell Stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45NM Technology PDF available

Author(s): K. Dhanumjaya | M. Sudha | MN.Giri Prasad | K.Padmaraju
Volume: 3
Issue: 2
Year: 2012
Bus Encoder for Crosstalk Avoidance in RLC Modeled Interconnects PDF available

Author(s): G. Nagendra Babu | Deepika Agarwal | B. K. Kaushik | S. K. Manhas
Volume: 3
Issue: 2
Year: 2012
Finite State Machine based Vending Machine Controller with Auto-Billing Features PDF available

Author(s): Ana Monga | Balwinder Singh
Volume: 3
Issue: 2
Year: 2012
A Systemc/Simulink Co-Simulation Environment of the JPEG Algorithm PDF available

Author(s): Walid Hassairi | Moncef Bousselmi | Mohamed Abid | Carlos Valderrama
Volume: 3
Issue: 2
Year: 2012
Analog VLSI Implementation of Neural Network Architecture for Signal Processing PDF available

Author(s): Neeraj Chasta | Sarita Chouhan | Yogesh Kumar
Volume: 3
Issue: 2
Year: 2012
Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design PDF available

Author(s): Subodh Wairya | Rajendra Kumar Nagaria | Sudarshan Tiwari
Volume: 3
Issue: 2
Year: 2012
VHDL Design for Image Segmentation using Gabor filter for Disease Detection PDF available

Author(s): Rucha R. Thakur | Swati R. Dixit | A.Y.Deshmukh
Volume: 3
Issue: 2
Year: 2012
Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA PDF available

Author(s): Neenu Joseph | P Nirmal Kumar
Volume: 3
Issue: 2
Year: 2012
Design and test challenges in Nano-scale analog and mixed CMOS technology PDF available

Author(s): Mouna Karmani | Chiraz Khedhiri | Belgacem Hamdi
Volume: 2
Issue: 2
Year: 2011
A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEM PDF available

Author(s): Dayadi.Lakshmaiah | Dr.M.V.Subramanyam | Dr.K.Sathaya Prasad
Volume: 2
Issue: 2
Year: 2011
A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS PDF available

Author(s): Chiraz Khedhiri | Mouna Karmani | Belgacem Hamdi
Volume: 2
Issue: 2
Year: 2011
A BUS ENCODING TO REDUCE CROSSTALK NOISE EFFECT IN SYSTEM ON CHIP PDF available

Author(s): J.Venkateswara Rao | A.V.N.Tilak
Volume: 2
Issue: 2
Year: 2011
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER PDF available

Author(s): Sudakar S. Chauhan | S. Manabala | S.C. Bose | R. Chandel
Volume: 2
Issue: 2
Year: 2011
NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS PDF available

Author(s): Subodh Wairya | Rajendra Kumar Nagaria | Sudarshan Tiwari
Volume: 2
Issue: 2
Year: 2011
PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED PDF available

Author(s): Sreenivasa Rao.Ijjada | Ayyanna.G | G.Sekhar Reddy | Dr.V.Malleswara Rao
Volume: 2
Issue: 2
Year: 2011
Design of optimized Interval Arithmetic Multiplier PDF available

Author(s): Rajashekar B.Shettar | Dr.R.M.Banakar
Volume: 2
Issue: 2
Year: 2011
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-m technology scale PDF available

Author(s): M.Sumathi | S.Malarvizhi
Volume: 2
Issue: 2
Year: 2011
Minimization of Handoff Latency by Co-ordinate Evaluation Method Using GPS Based Map PDF available

Author(s): Debabrata Sarddar | Joydeep Banerjee | Souvik Kumar Saha | Tapas Jana | Utpal Biswas | M.K. Naskar
Volume: 1
Issue: 2
Year: 2010
Two Dimensional Modeling of Nonuniformly Doped MESFET Under Illumination PDF available

Author(s): B.K.Mishra | Lochan Jolly | Kalawati Patil
Volume: 1
Issue: 2
Year: 2010
Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology PDF available

Author(s): Ujwala A. Belorkar | S.A.Ladhake
Volume: 1
Issue: 2
Year: 2010
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication Systems PDF available

Author(s): Rajesh Mehra | Swapna Devi
Volume: 1
Issue: 2
Year: 2010
A Multi-Objective Perspective for Operator Scheduling Using Finegrained DVS Architectures PDF available

Author(s): Rajdeep Mukherjee | Priyankar Ghosh | Pallab Dasgupta | Ajit Pal
Volume: 4
Issue: 1
Year: 2013
Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data PDF available

Author(s): Vaishali Dhare | Usha Mehta
Volume: 4
Issue: 1
Year: 2013
A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric PDF available

Author(s): Anil Yadav | Gayatri Mehta | Alex K. Jones | Justin Stander
Volume: 4
Issue: 1
Year: 2013
Ternary Tree Asynchronous Interconnect Network for GALS' SOC PDF available

Author(s): Vivek E. Khetade | S.S. Limaye
Volume: 4
Issue: 1
Year: 2013
Dual Field Dual Core Secure Cryptoprocessor on FPGA Platform PDF available

Author(s): C. Veeraraghavan | K. Rajendran
Volume: 4
Issue: 1
Year: 2013
A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology PDF available

Author(s): Tarun Kr. Gupta | Kavita Khare
Volume: 4
Issue: 1
Year: 2013
Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data PDF available

Author(s): Sunita M.S | Kanchana Bhaaskaran V.S
Volume: 4
Issue: 1
Year: 2013
Realization of Transmitter and Receiver Architecture for Downlink Channels in 3-GPP LTE PDF available

Author(s): S. Syed Ameer Abbas | J. Rahumath Nisha | M. Beril Sahaya Mary | S. J. Thiruvengadam
Volume: 4
Issue: 1
Year: 2013
An Efficient CNTFET Based 7-Input Minority Gate PDF available

Author(s): Samira Shirinabadi Farahani | Ronak Zarhoun | Mohammad Hossein Moaiyeri | Keivan Navi
Volume: 4
Issue: 1
Year: 2013
Reduction of Bus Transition for Compressed Code Systems PDF available

Author(s): S. R. Malathi | R. Ramya Asmi
Volume: 4
Issue: 1
Year: 2013
Design Approach for Fault Tolerance in FPGA Architecture PDF available

Author(s): Ms. Shweta S. Meshram | Ujwala A. Belorkar
Volume: 2
Issue: 1
Year: 2011
Design of a high frequency low voltage CMOS operational amplifier PDF available

Author(s): Priyanka Kakoty
Volume: 2
Issue: 1
Year: 2011
Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETs PDF available

Author(s): Neha Sharan | Ashwani K.Rana
Volume: 2
Issue: 1
Year: 2011
Design and Implementation of Area and Power Optimised Novel Scanflop PDF available

Author(s): R.Jayagowri | K.S.Gurumurthy
Volume: 2
Issue: 1
Year: 2011
Physical Scaling Limits of FinFET Structure: A Simulation Study PDF available

Author(s): Gaurav Saini | Ashwani K Rana
Volume: 2
Issue: 1
Year: 2011
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates PDF available

Author(s): K. Ragini | M. Satyam | B.C. Jinaga
Volume: 1
Issue: 1
Year: 2010
QoS Based Capacity Enhancement for WCDMA Network with Coding Scheme PDF available

Author(s): K.AYYAPPAN | R. KUMAR
Volume: 1
Issue: 1
Year: 2010
Design of A Low Power Low Voltage CMOS Opamp PDF available

Author(s): Ratul Kr. Baruah
Volume: 1
Issue: 1
Year: 2010
Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology PDF available

Author(s): Ms. Ujwala A. Belorkar | S.A.Ladhake
Volume: 2
Issue: 1
Year: 2011
Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function PDF available

Author(s): Deepesh Ranka | Ashwani K. Rana | Rakesh Kumar Yadav | Kamalesh Yadav | Devendra Giri
Volume: 2
Issue: 1
Year: 2011
High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor PDF available

Author(s): Ashkan Khatir | Shaghayegh Abdolahzadegan | Iman Mahmoudi
Volume: 2
Issue: 1
Year: 2011
Design and Analysis of Second and Third Order PLL at 450MHz PDF available

Author(s): B. K. Mishra | Sandhya Save | Swapna Patil
Volume: 2
Issue: 1
Year: 2011
Arithmetic Operations in Multi-Valued Logic PDF available

Author(s): Vasundara Patel k s | k s gurumurthy
Volume: 1
Issue: 1
Year: 2010
A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate PDF available

Author(s): Sadhana Sharma | Abhay Vidyarthi | Shyam Akashe
Volume: 04
Issue: 03
Year: 2013
Design and Implementation of Car Parking System on FPGA PDF available

Author(s): Ramneet Kaur | Balwinder Singh
Volume: 04
Issue: 03
Year: 2013
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit PDF available

Author(s): Rakshith Saligram | Shrihari Shridhar Hegde | Shashidhar A Kulkarni | H.R.Bhagyalakshmi | M.K. Venkatesha
Volume: 04
Issue: 03
Year: 2013
CMOS Low Power Cell Library for Digital Design PDF available

Author(s): Kanika Kaur | Arti Noor
Volume: 04
Issue: 03
Year: 2013
Crosstalk Minimization for Coupled RLC Interconnects Using Bidirectional Buffer and Shield Insertion PDF available

Author(s): Damanpreet Kaur | V.Sulochana
Volume: 04
Issue: 03
Year: 2013
Low Power Dual Edge - Triggered Static D Flip-Flop PDF available

Author(s): Anurag | Gurmohan Singh | Gurmohan Singh
Volume: 04
Issue: 03
Year: 2013
Hardware Efficient Scaling Free Vectoring and Rotational Cordic for DSP Applications PDF available

Author(s): Anita Jain | Kavita Khare
Volume: 04
Issue: 03
Year: 2013
Enhancing Multiplier Speed in Fast Fourier Transform Based on Vedic Mathematics PDF available

Author(s): R.P.Meenaakshi Sundari | D.Subathra | M.S.Dhanalaxmi
Volume: 04
Issue: 03
Year: 2013
Power Efficient Carry Propagate Adder PDF available

Author(s): Laxmi Kumre | Ajay Somkuwar | Ganga Agnihotri
Volume: 04
Issue: 03
Year: 2013
Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter PDF available

Author(s): Arun Kumar Sunaniya | Kavita Khare
Volume: 04
Issue: 03
Year: 2013
Design and Performance Analysis of ZBT SRAM Controller PDF available

Author(s): Smriti Sharma | Balwinder Singh
Volume: 04
Issue: 03
Year: 2013
Design of a Programmable Low Power Low Drop-Out Regulator PDF available

Author(s): Jayanthi Vanama | G.L.Sampoorna
Volume: 04
Issue: 03
Year: 2013
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme PDF available

Author(s): Majed ValadBeigi | Farshad Safaei | Bahareh Pourshirazi
Year: 2012
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