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VLSI Design

ISSN: 1065--514X
Publisher: Hindawi Publishing Corporation


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Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Author(s): Srilata Raman | C. L. Liu | Larry G. Jones
Volume: 4
Issue: 4
Year: 1996
DP-FPGA: An FPGA Architecture Optimized for Datapaths

Author(s): Don Cherepacha | David Lewis
Volume: 4
Issue: 4
Year: 1996
A Timing-Driven Partitioning System for Multiple FPGAs

Author(s): Kalapi Roy | Carl Sechen
Volume: 4
Issue: 4
Year: 1996
A Sea-of-Gates Style FPGA Placement Algorithm

Author(s): Kalapi Roy | Bingzhong (David) Guan | Carl Sechen
Volume: 4
Issue: 4
Year: 1996
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Author(s): Stephen Brown | Muhammad Khellah | Guy Lemieux
Volume: 4
Issue: 4
Year: 1996
Field-Programmable Gate Arrays

Author(s): Dinesh Bhatia
Volume: 4
Issue: 4
Year: 1996
On Some Properties of the Star Graph

Author(s): Ke Qiu | Selim G. Akl
Volume: 2
Issue: 4
Year: 1995
Designing Interconnection Networks forMulti-level Packaging

Author(s): M. T. Raghunath | Abhiram Ranade
Volume: 2
Issue: 4
Year: 1995
Trade-Off Considerations in Designing Efficient VLSIFeasible Interconnection Networks

Author(s): S. Q. Zheng | B. Cong | S. Bettayeb
Volume: 2
Issue: 4
Year: 1995
Least Common Ancestor Networks

Author(s): Isaac D. Scherson | Chi-Kai Chien
Volume: 2
Issue: 4
Year: 1995
Embeddings into Hyper Petersen Networks: YetAnother Hypercube-Like Interconnection Topology

Author(s): Sajal K. Das | Sabine Öhring | Amit K. Banerjee
Volume: 2
Issue: 4
Year: 1995
The Cost of Adaptivity and Virtual Lanes in aWormhole Router

Author(s): Kazuhiro Aoyama | Andrew A. Chien
Volume: 2
Issue: 4
Year: 1995
The STC104 Packet Routing Chip

Author(s): Peter W. Thompson | Julian D. Lewis
Volume: 2
Issue: 4
Year: 1995
Design of Components for a Low Cost CombiningSwitch

Author(s): Susan R. Dickey | Richard Kenner
Volume: 2
Issue: 4
Year: 1995
Guest Editor's Introduction

Author(s): Pradip K. Srimani
Volume: 2
Issue: 4
Year: 1995
Integrated Test Solutions for a System DesignEnvironment

Author(s): Kevin T. Kornegay | Robert W. Brodersen
Volume: 1
Issue: 4
Year: 1994
An Approach for Self-Checking Realization ofInteracting Finite State Machines

Author(s): Fadi Busaba | Parag K. Lala
Volume: 1
Issue: 4
Year: 1994
STD Architecture: A Practical Approach to TestM-Bits Random Access Memories

Author(s): Rochit Rajsuman | Kamal Rajkanan
Volume: 1
Issue: 4
Year: 1994
Empirical Bounds on Fault Coverage LossDue to LFSR Aliasing

Author(s): Warren H. Debany | Mark J. Gorniak | Anthony R. Macera | Daniel E. Daskiewich | Kevin A. Kwiat | Heather B. Dussault
Volume: 1
Issue: 4
Year: 1994
Partial Reset: An Alternative DFT Approach

Author(s): Ben Mathew | Daniel G. Saab
Volume: 1
Issue: 4
Year: 1994
Optimal Testing and Design of Adders

Author(s): Michael J. Batek | John P. Hayes
Volume: 1
Issue: 4
Year: 1994
Resolution Enhancement in IDDQ Testingfor Large ICs

Author(s): Yashwant K. Malaiya | Anura P. Jayasumana | Carol Q. Tong | Sankaran M. Menon
Volume: 1
Issue: 4
Year: 1994
Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS& BiCMOS Circuits

Author(s): M. O. Esonu | D. Al-Khalili | C. Rozon
Volume: 1
Issue: 4
Year: 1994
Special Issue on Digital Hardware Testing

Author(s): Rochit Rajsuman
Volume: 1
Issue: 4
Year: 1994
Guest Editor's Introduction

Author(s): Lech Jóźwiak
Volume: 3
Issue: 3-4
Year: 1995
Decomposition and Reduction: GeneralProblem-Solving Paradigms

Author(s): Michal Servít | Jan Zamazal
Volume: 3
Issue: 3-4
Year: 1995
Decomposition of Sequential Behavior UsingInterface Specification and Complementation

Author(s): Kamlesh Rath | Venkatesh Choppella | Steven D. Johnson
Volume: 3
Issue: 3-4
Year: 1995
PARTIF: Interactive System-level Partitioning

Author(s): Tarek Ben Ismail | Kevin O'Brien | Ahmed Jerraya
Volume: 3
Issue: 3-4
Year: 1995
A New Design Methodology for Two-DimensionalLogic Arrays

Author(s): Ning Song | Marek A. Perkowski | Malgorzata Chrzanowska-Jeske | Andisheh Sarabi
Volume: 3
Issue: 3-4
Year: 1995
Multi-Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

Author(s): Marek A. Perkowski | Malgorzata Chrzanowska-Jeske | Andisheh Sarabi | Ingo Schäfer
Volume: 3
Issue: 3-4
Year: 1995
A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis

Author(s): Tadeusz Łuba | Henry Selvaraj
Volume: 3
Issue: 3-4
Year: 1995
Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

Author(s): Frank Volf | Lech Jóźwiak | Mario Stevens
Volume: 3
Issue: 3-4
Year: 1995
FSM Decomposition and Functional Verification ofFSM Networks

Author(s): Zafar Hasan | Maciej J. Ciesielski
Volume: 3
Issue: 3-4
Year: 1995
General Decomposition and Its Use in Digital Circuit Synthesis

Author(s): Lech Jóźwiak
Volume: 3
Issue: 3-4
Year: 1995
Erratum

Volume: 4
Issue: 3
Year: 1996
Current Testing of CMOS Combinational Circuits withSingle Floating Gate Defects

Author(s): Victor H. Champac | Joan Figueras
Volume: 5
Issue: 3
Year: 1997
IDDQ Testing Experiments for Various CMOS LogicDesign Structures

Author(s): A. Toukmaji | R. Helms | R. Makki | W. Mikhail | R. Toole
Volume: 5
Issue: 3
Year: 1997
IDDQ Detectable Bridges in Combinational CMOS Circuits

Author(s): E. Isern | J. Figueras
Volume: 5
Issue: 3
Year: 1997
Application of Dynamic Supply Current Monitoring toTesting Mixed-Signal Circuits

Author(s): Mahmoud A. Al-Qutayri | Peter R. Shepherd
Volume: 5
Issue: 3
Year: 1997
Advancements in Power Supply Current Testing

Author(s): Rafic Z. Makki
Volume: 5
Issue: 3
Year: 1997
A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

Author(s): S. Bandyopadhyay | A. Sengupta | B. B. Bhattacharya
Volume: 4
Issue: 3
Year: 1996
A Modified Approach to Test Plan Generation for Combinational Logic Blocks

Author(s): Anupam Basu | Dilip K. Banerji | Amit Basu | T. C. Wilson | Jay C. Majithia
Volume: 4
Issue: 3
Year: 1996
Fault Modeling of ECL for High Fault Coverage of Physical Defects

Author(s): Sankaran M. Menon | Yashwant K. Malaiya | Anura P. Jayasumana
Volume: 4
Issue: 3
Year: 1996
Switch-level Differential Fault Simulation of MOS VLSI Circuits

Author(s): Evstratios Vandris | Gerald Sobelman
Volume: 4
Issue: 3
Year: 1996
On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

Author(s): M. Srinivas | L. M. Patnaik
Volume: 4
Issue: 3
Year: 1996
Closed Form Aliasing Probability For Q-ary Symmetric Errors

Author(s): Geetani Edirisooriya
Volume: 4
Issue: 3
Year: 1996
HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Author(s): Kyuchull Kim | Kewal K. Saluja
Volume: 4
Issue: 3
Year: 1996
A Novel Path Delay Fault Simulator Using Binary Logic

Author(s): Ananta K. Majhi | James Jacob | Lalit M. Patnaik
Volume: 4
Issue: 3
Year: 1996
PGEN: A Novel Approach to Sequential Circuit Test Generation

Author(s): Wen-Ben Jone | Nigam Shah | Anita Gleason | Sunil R. Das
Volume: 4
Issue: 3
Year: 1996
Guest Editorial

Author(s): Sunil R. Das
Volume: 4
Issue: 3
Year: 1996
Modular Scheme for Designing Special PurposeAssociative Memories and Beyond

Author(s): A. R. Hurson | S. Pakzad
Volume: 2
Issue: 3
Year: 1994
An Improved Data Flow Architecture for LogicSimulation Acceleration

Author(s): A. Mahmood | J. Herath | J. Jayasumana
Volume: 2
Issue: 3
Year: 1994
SEGMA: A Simulated Evolution Gate-Matrix LayoutAlgorithm

Author(s): Chi-Yu Mao | Yu Hen Hu
Volume: 2
Issue: 3
Year: 1994
TOPS: A Target-Oriented Partial Scan DesignPackage Based on Simulated Annealing

Author(s): C. P. Ravikumar | H. Rasheed
Volume: 2
Issue: 3
Year: 1994
Techniques for Self-Checking Combinational LogicSynthesis

Author(s): Fadi Busaba | Parag K. Lala
Volume: 2
Issue: 3
Year: 1994
An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits

Author(s): Hyung K. Lee | Dong S. Ha
Volume: 2
Issue: 3
Year: 1994
Partitioning Techniques for Built-In Self-Test Design

Author(s): Chien-In Henry Chen
Volume: 2
Issue: 3
Year: 1994
Block-Level Logic Extraction from CMOS VLSILayouts

Author(s): Inderpreet Bhasin | Joseph G. Tront
Volume: 1
Issue: 3
Year: 1994
An Optimum Channel Routing Algorithm in theKnock-knee Diagonal Model

Author(s): Xiaoyu Song
Volume: 1
Issue: 3
Year: 1994
Using PDM on Multiport Memory Allocationin Data Path

Author(s): Chien-In Henry Chen
Volume: 1
Issue: 3
Year: 1994
Fast Algorithms to Partition Simple RectilinearPolygons

Author(s): San-Yuan Wu | Sartaj Sahni
Volume: 1
Issue: 3
Year: 1994
Cluster Partitioning Techniques for Data PathSynthesis

Author(s): Chien-In Henry Chen | Gerald Sobelman
Volume: 1
Issue: 3
Year: 1994
Layout Modeling and Design Space Exploration in Pss1 System

Author(s): Fur-Shing Tsai | Yu-Chin Hsu
Volume: 5
Issue: 2
Year: 1997
Datapath Optimization Using Layout Information: An Empirical Study

Author(s): Allen C.-H. Wu
Volume: 5
Issue: 2
Year: 1997
Taking Thermal Considerations Into Account DuringHigh-Level Synthesis

Author(s): Jen-Pin Weng | Alice C. Parker
Volume: 5
Issue: 2
Year: 1997
Module Selection in Microarchitectural Synthesis forMultiple Critical Constraint Satisfaction

Author(s): Ian G. Harris | Alex Orailoğlu
Volume: 5
Issue: 2
Year: 1997
RT Component Sets for High-Level Design Applications

Author(s): Nikil D. Dutt | Pradip K. Jha
Volume: 5
Issue: 2
Year: 1997
Statistical Module Level Area and Delay Estimation

Author(s): Akhilesh Tyagi
Volume: 5
Issue: 2
Year: 1997
Effective Coupling Between Logic Synthesis and LayoutTools for Synthesis of Area and Speed-Efficient Circuits

Author(s): Mandalagiri S. Chandrasekhar | Robert H. McCharles | David E. Wallace
Volume: 5
Issue: 2
Year: 1997
Combining Technology Mapping With Layout

Author(s): Massoud Pedram | Narasimha Bhat | Ernest S. Kuh
Volume: 5
Issue: 2
Year: 1997
Linking Behavioral, Structural, and Physical Modelsof Hardware

Author(s): Fadi J. Kurdahi
Volume: 5
Issue: 2
Year: 1997
Hardware Design Rule Checker Using a CAM Architecture

Author(s): Seokjin Kim | Ramalingam Sridhar
Volume: 4
Issue: 2
Year: 1996
The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Author(s): Neil J. Howard | Andrew M. Tyrrell | Nigel M. Allinson
Volume: 4
Issue: 2
Year: 1996
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

Author(s): Sungho Kang | Youngmin Hur | Stephen A. Szygenda
Volume: 4
Issue: 2
Year: 1996
An Integrated Hardware Array for Very High Speed Logic Simulation

Author(s): E. Scott Fehr | Stephen A. Szygenda | Granville E. Ott
Volume: 4
Issue: 2
Year: 1996
An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations

Author(s): Ausif Mahmood | William I. Baker
Volume: 4
Issue: 2
Year: 1996
Hardware Accelerators for VLSI Design

Author(s): Ausif Mahmood
Volume: 4
Issue: 2
Year: 1996
Formulation of Macroscopic TransportModels for Numerical Simulationof Semiconductor Devices

Author(s): Edwin C. Kan | Zhiping Yu | Robert W. Dutton | Datong Chen | Umberto Ravaioli
Volume: 3
Issue: 2
Year: 1995
Resonant Tunneling in the QuantumHydrodynamic Model

Author(s): Carl L. Gardner
Volume: 3
Issue: 2
Year: 1995
Electron Transport Using the QuantumCorrected Hydrodynamic Equations

Author(s): J. P. Kreskovsky | H. L. Grubin
Volume: 3
Issue: 2
Year: 1995
2-D Simulation of Quantum Effects in SmallSemiconductor Devices Using QuantumHydrodynamic Equations

Author(s): Jing-Rong Zhou | David K. Ferry
Volume: 3
Issue: 2
Year: 1995
Mixed-RKDG Finite Element Methodsfor the 2-D Hydrodynamic Modelfor Semiconductor Device Simulation

Author(s): Zhangxin Chen | Bernardo Cockburn | Joseph W. Jerome | Chi-Wang Shu
Volume: 3
Issue: 2
Year: 1995
The Response of the Hydrodynamic Modelto Heat Conduction, Mobility,and Relaxation Expressions

Author(s): Joseph W. Jerome | Chi-Wang Shu
Volume: 3
Issue: 2
Year: 1995
On the Structure and Closure-Conditionof the Hydrodynamic Model

Author(s): Massimo Rudan | Giorgio Baccarani
Volume: 3
Issue: 2
Year: 1995
Hydrodynamic Models of SemiconductorElectron Transport at High Fields

Author(s): M. G. Ancona
Volume: 3
Issue: 2
Year: 1995
Classical and Quantum Hydrodynamic DeviceModels and Energy Transport

Author(s): Joseph W. Jerome
Volume: 3
Issue: 2
Year: 1995
Channel Density Minimization by Pin Permutation

Author(s): Yang Cai | D. F. Wong | Jason Cong
Volume: 2
Issue: 2
Year: 1994
On the Minimum Density Interconnection TreeProblem

Author(s): C. J. Alpert | J. Cong | A. B. Kahng | G. Robins | M. Sarrafzadeh
Volume: 2
Issue: 2
Year: 1994
Area Optimization of Slicing Floorplans in Parallel

Author(s): Cheng-Hsi Chen | Ioannis G. Tollis
Volume: 2
Issue: 2
Year: 1994
A New Clustering Method Based onGeneral Connectivity

Author(s): Wenjun Zhuang | Yong Ching Lim | Ganesh Samudra | Neng Yan
Volume: 2
Issue: 2
Year: 1994
An Effective Solution to the LinearPlacement Problem

Author(s): Youssef Saab | Cheng-Hua Chen
Volume: 2
Issue: 2
Year: 1994
Pioneer: A New Tool for Coding of Multi-Level FiniteState Machines Based on Evolution Programming

Author(s): S. Muddappa | R. Z. Makki | Z. Michalewicz | S. Isukapalli
Volume: 2
Issue: 2
Year: 1994
Technology Mapping for FPGA Using GeneralizedFunctional Decomposition

Author(s): Kuo-Hua Wang | Cheng Chen | Ting Ting Hwang
Volume: 2
Issue: 2
Year: 1994
Preface

Author(s): Si-Qing Zheng | Dian Zhou
Volume: 2
Issue: 2
Year: 1994
Distributed and Parallel Demand Driven LogicSimulation Algorithms

Author(s): K. Subramanian | M. Zargham
Volume: 1
Issue: 2
Year: 1994
Geometric Design Rule Check of VLSI Layouts inDistributed Computing Environment

Author(s): S. K. Nandy
Volume: 1
Issue: 2
Year: 1994
Geometric Design Rule Check of VLSI Layouts inMesh Connected Processors

Author(s): S. K. Nandy | R. B. Panwar
Volume: 1
Issue: 2
Year: 1994
A VHDL Based Expert System for HardwareSynthesis

Author(s): Sajjan G. Shiva | Judit U. Jones
Volume: 1
Issue: 2
Year: 1994
Building Rectangular Floorplans–A GraphTheoretical Approach

Author(s): Marwan A. Jabri
Volume: 1
Issue: 2
Year: 1994
High-Level Graphical Abstraction in Digital Design

Author(s): Murray W. Pearson | Paul J. Lyons | Mark D. Apperley
Volume: 5
Issue: 1
Year: 1996
Zener Zap Anti-Fuse Trim in VLSI Circuits

Author(s): Donald T. Comer
Volume: 5
Issue: 1
Year: 1996
TOGAPS: A Testability Oriented GeneticAlgorithm For Pipeline Synthesis

Author(s): C. P. Ravikumar | V. Saxena
Volume: 5
Issue: 1
Year: 1996
A New Theory for Testability-Preserving Optimization ofCombinational Circuits

Author(s): Jiabi Zhu | Mostafa Abd-El-Barr | Carl McCrosky
Volume: 5
Issue: 1
Year: 1996
Improving Path Sensitizability ofCombinational Circuits

Author(s): Bhanu Kapoor | V. S. S. Nair
Volume: 5
Issue: 1
Year: 1996
A Greedy Algorithm for Over-The-Cell Channel Routing

Author(s): Gudni Gudmundsson | Simeon Ntafos
Volume: 5
Issue: 1
Year: 1996
Greedy Segmented Channel Router

Author(s): Dinesh Bhatia | V. Shankar
Volume: 5
Issue: 1
Year: 1996
An Efficient and Fast Algorithm for RoutingOver the Cells

Author(s): Kuo-En Chang | Sei-Wang Chen
Volume: 5
Issue: 1
Year: 1996
Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

Author(s): B. Majumdar | V. V. Ramakrishna | P. S. Dey | A. K. Majumdar
Volume: 4
Issue: 1
Year: 1996
Design and Implementation of a Low Power Ternary Full Adder

Author(s): A. Srivastava | K. Venkatapathy
Volume: 4
Issue: 1
Year: 1996
Integration of SPICE with TEK LV500 ASIC Design Verification System

Author(s): A. Srivastava | S. R. Palavali
Volume: 4
Issue: 1
Year: 1996
Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

Author(s): Ausif Mahmood
Volume: 4
Issue: 1
Year: 1996
Minimum-Cost Node-Disjoint Steiner Trees in Series-Parallel Networks

Author(s): Sunil Chopra | Kalyan T. Talluri
Volume: 4
Issue: 1
Year: 1996
An Efficient Algorithm for the Split K-Layer Circular Topological Via Minimization Problem

Author(s): J. S. Huang | Y. H. Chin
Volume: 4
Issue: 1
Year: 1996
Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs

Author(s): D. Bhagavathi | H. Gurla | S. Olariu | J. L. Schwing | J. Zhang
Volume: 4
Issue: 1
Year: 1996
Nearly Balanced Quad List Quad Tree -A Data Structure for VLSI Layout Systems

Author(s): Pei-Yung Hsiao
Volume: 4
Issue: 1
Year: 1996
An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment

Author(s): Jin-Tai Yan | Pei-Yung Hsiao
Volume: 4
Issue: 1
Year: 1996
A Multi-Terminal Net Router for Field-Programmable Gate Arrays

Author(s): Dinesh Bhatia | Amit Chowdhary
Volume: 4
Issue: 1
Year: 1996
New Methods for the Construction of TestCases for Partitioning Heuristics

Author(s): Youssef Saab
Volume: 3
Issue: 1
Year: 1995
A Comparative Study of SynchronousClocking Schemes for VLSI Based Systems

Author(s): Ahmed El-Amawy | Umasankar Maheshwar
Volume: 3
Issue: 1
Year: 1995
A Comparison of Bit Serialand Bit Parallel DCT Designs

Author(s): David Crook | John Fulcher
Volume: 3
Issue: 1
Year: 1995
Input/Output Pad Placement Problem

Author(s): Khaled Al-Zamel | Mukkai S. Krishnamoorthy
Volume: 3
Issue: 1
Year: 1995
Performance and Area Optimization of VLSISystems Using Genetic Algorithms

Author(s): Xiao-Dong Wang | Tom Chen
Volume: 3
Issue: 1
Year: 1995
Flipping Modules to MinimizeMaximum Wire Length

Author(s): Kyunrak Chong | Sartaj Sahni
Volume: 3
Issue: 1
Year: 1995
An ILP Solution for Optimum Scheduling, Moduleand Register Allocation, and OperationBinding in Datapath Synthesis

Author(s): T. C. Wilson | N. Mukherjee | M. K. Garg | D. K. Banerji
Volume: 3
Issue: 1
Year: 1995
Applying Neural Networks to Findthe Minimum Cost Coverageof a Boolean Function

Author(s): Pong P. Chu
Volume: 3
Issue: 1
Year: 1995
Cell Generator-Based Technology Mappingby Constructive Tree-Matchingand Dynamic Covering

Author(s): Martin Lefebvre | Cliff Liem
Volume: 3
Issue: 1
Year: 1995
Analysis and Characterization of State AssignmentTechniques for Sequential Machines

Author(s): R. Z. Makki | S. Su
Volume: 2
Issue: 1
Year: 1994
Temporal Logic Based Hierarchical Test Generationfor Sequential VLSI Circuits

Author(s): Anand V. Hudli | Raghu V. Hudli
Volume: 2
Issue: 1
Year: 1994
On Channel Routing Problems WithInterchangeable Terminals

Author(s): Spyros Tragoudas
Volume: 2
Issue: 1
Year: 1994
High Throughput Error Control Using Parallel CRC

Author(s): Andrzej Sobski | Alexander Albicki
Volume: 2
Issue: 1
Year: 1994
Register-Transfer Synthesis of Pipelined Data Paths

Author(s): Nohbyung Park | Fadi J. Kurdahi
Volume: 2
Issue: 1
Year: 1994
Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

Author(s): Peter J. Ashenden | Henry Detmold | Wayne S. McKeen
Volume: 2
Issue: 1
Year: 1994
Computer-Aided Testing Systems: Evaluation andBenchmark Circuits

Author(s): Samiha Mourad
Volume: 1
Issue: 1
Year: 1993
Coverage of Node Shorts Using Internal Access andEquivalence Classes

Author(s): Warren H. Debany
Volume: 1
Issue: 1
Year: 1993
Conditional Disconnection Probability in Star Graphs

Author(s): Walid Najjar | Pradip K. Srimani
Volume: 1
Issue: 1
Year: 1993
Analysis and Design of Regular Structures for RobustDynamic Fault Testability

Author(s): Michael J. Bryan | Srinivas Devadas | Kurt Keutzer
Volume: 1
Issue: 1
Year: 1993
Built-In Self-Test: Milestones and Challenges

Author(s): Jacob Savir | Paul H. Bardell
Volume: 1
Issue: 1
Year: 1993
Theory, Analysis and Implementation of an On-LineBIST Technique

Author(s): Rajiv Sharma | Kewal K. Saluja
Volume: 1
Issue: 1
Year: 1993
Overlapped Subarray Segmentation: An Efficient TestMethod for Cellular Arrays

Author(s): Earl E. Swartzlander | Miroslaw Malek
Volume: 1
Issue: 1
Year: 1993
About the Editor in Chief and the Guest Editor

Volume: 1
Issue: 1
Year: 1993
Guest Editorial

Author(s): Sunil R. Das
Volume: 1
Issue: 1
Year: 1993
Editorial

Volume: 1
Issue: 1
Year: 1993
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Author(s): David H. K. Hoe | L. P. Deepthi Bollepalli | Chris D. Martinez
Volume: 2013
Year: 2013
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Author(s): Shipra Upadhyay | R. K. Nagaria | R. A. Mishra
Volume: 2013
Year: 2013
Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Author(s): Bisrat Tafesse | Venkatesan Muthukumar
Volume: 2013
Year: 2013
Ingredients of Adaptability: A Survey of Reconfigurable Processors

Author(s): Anupam Chattopadhyay
Volume: 2013
Year: 2013
Power-Driven Global Routing for Multisupply Voltage Domains

Author(s): Tai-Hsuan Wu | Azadeh Davoodi | Jeffrey T. Linderoth
Volume: 2013
Year: 2013
Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection

Author(s): Francesco Colonna | Mariagrazia Graziano | Mario R. Casu | Xiaolu Guo | Maurizio Zamboni
Volume: 2013
Year: 2013
Design a Bioamplifier with High CMRR

Author(s): Yu-Ming Hsiao | Miin-Shyue Shiau | Kuen-Han Li | Jing-Jhong Hou | Heng-Shou Hsu | Hong-Chong Wu | Don-Gey Liu
Volume: 2013
Year: 2013
A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

Author(s): Ching-Lung Su | Tse-Min Chen | Kuo-Hsuan Wu
Volume: 2013
Year: 2013
A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

Author(s): Hou-Ming Chen | Robert C. Chang | Kuang-Hao Lin
Volume: 2013
Year: 2013
Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Author(s): Carna Radojicic | Christoph Grimm | Florian Schupfer | Michael Rathmair
Volume: 2013
Year: 2013
Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver

Author(s): Diego Javier Reinoso Chisaguano | Minoru Okada
Volume: 2013
Year: 2013
High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

Author(s): Ting-Li Chu | Sin-Hong Yu | Chorng-Sii Hwang
Volume: 2013
Year: 2013
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Author(s): Tinoosh Mohsenin | Houshmand Shirani-mehr | Bevan M. Baas
Volume: 2013
Year: 2013
A 0.6-V to 1-V Audio Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

Author(s): Liyuan Liu | Dongmei Li | Zhihua Wang
Volume: 2013
Year: 2013
Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera

Author(s): Yu-Cheng Fan | Yi-Feng Chiang
Volume: 2013
Year: 2013
Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

Author(s): Shadi Traboulsi | Valerio Frascolla | Nils Pohl | Josef Hausner | Attila Bilgic
Volume: 2013
Year: 2013
A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Author(s): Lilia Zaourar | Yann Kieffer | Chouki Aktouf
Volume: 2012
Year: 2012
A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

Author(s): Sheng-Chieh Huang | Hui-Min Wang | Wei-Yu Chen
Volume: 2012
Year: 2012
Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

Author(s): Chia-Hao Fang | I-tao Lung | Chih-Peng Fan
Volume: 2012
Year: 2012
Line Search-Based Inverse Lithography Technique for Mask Design

Author(s): Xin Zhao | Chris Chu
Volume: 2012
Year: 2012
Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Author(s): Leonardo Palacios-Luengas | Gonzalo Isaac Duchen-Sánchez | José Luis Aragón-Vera | Rubén Vázquez-Medina
Volume: 2012
Year: 2012
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Author(s): Maurizio Martina | Muhammad Shafique | Andrey Norkin
Volume: 2012
Year: 2012
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Author(s): Guido Masera | Amer Baghdadi | Frank Kienle | Christophe Moy
Volume: 2012
Year: 2012
Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

Author(s): Maher Assaad | Mohammed H. Alser
Volume: 2012
Year: 2012
Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Author(s): Khaled Jerbi | Mickaël Raulet | Olivier Déforges | Mohamed Abid
Volume: 2012
Year: 2012
FastRoute: An Efficient and High-Quality Global Router

Author(s): Min Pan | Yue Xu | Yanheng Zhang | Chris Chu
Volume: 2012
Year: 2012
Flexible LDPC Decoder Architectures

Author(s): Muhammad Awais | Carlo Condo
Volume: 2012
Year: 2012
A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems

Author(s): Dionysios Diamantopoulos | Kostas Siozios | Sotiris Xydis | Dimitrios Soudris
Volume: 2012
Year: 2012
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors

Author(s): Yahya Jan | Lech Józwiak
Volume: 2012
Year: 2012
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Author(s): Paolo Meloni | Sebastiano Pomata | Giuseppe Tuveri | Simone Secchi | Luigi Raffo | Menno Lindwer
Volume: 2012
Year: 2012
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Author(s): Subodh Wairya | Rajendra Kumar Nagaria | Sudarshan Tiwari
Volume: 2012
Year: 2012
A Signature-Based Power Model for MPSoC on FPGA

Author(s): Roberta Piscitelli | Andy D. Pimentel
Volume: 2012
Year: 2012
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

Author(s): Emanuele Cannella | Onur Derin | Paolo Meloni | Giuseppe Tuveri | Todor Stefanov
Volume: 2012
Year: 2012
9T Full Adder Design in Subthreshold Region

Author(s): Shiwani Singh | Tripti Sharma | K. G. Sharma | B. P. Singh
Volume: 2012
Year: 2012
Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

Author(s): Zhen-dong Zhang | Bin Wu | Yu-mei Zhou | Xin Zhang
Volume: 2012
Year: 2012
CAD for Gigascale SoC Design and Verification Solutions

Author(s): Shiyan Hu | Zhuo Li | Yangdong Deng
Volume: 2011
Year: 2011
Efficient Resource Sharing Architecture for Multistandard Communication System

Author(s): T. Suresh | K. L. Shunmuganathan
Volume: 2011
Year: 2011
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Author(s): Subhra Dhar | Manisha Pattanaik | Poolla Rajaram
Volume: 2011
Year: 2011
Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

Author(s): Tareq Hasan Khan | Khan A. Wahid
Volume: 2011
Year: 2011
Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

Author(s): I. Hameem Shanavas | Ramaswamy Kannan Gnanamurthy
Volume: 2011
Year: 2011
A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Author(s): Guanyi Sun | Shengnan Xu | Xu Wang | Dawei Wang | Eugene Tang | Yangdong Deng | Sun Chan
Volume: 2011
Year: 2011
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

Author(s): Soumya Pandit | Chittaranjan Mandal | Amit Patra
Volume: 2011
Year: 2011
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Author(s): S. Jayanthy | M. C. Bhuvaneswari | Keesarapalli Sujitha
Volume: 2012
Year: 2012
A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Author(s): Tzung-Je Lee | Chua-Chin Wang
Volume: 2008
Year: 2008
Fine Control of Local Whitespace in Placement

Author(s): Jarrod A. Roy | David A. Papa | Igor L. Markov
Volume: 2008
Year: 2008
A Dependable Micro-Electronic Peptide Synthesizer Using Electrode Data

Author(s): H. G. Kerkhoff | X. Zhang | F. Mailly | P. Nouet | H. Liu | A. Richardson
Volume: 2008
Year: 2008
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme

Author(s): G. Seetharaman | B. Venkataramani | G. Lakshminarayanan
Volume: 2008
Year: 2008
Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test

Author(s): Yves Joannon | Vincent Beroulle | Chantal Robach | Smail Tedjini | Jean-Louis Carbonero
Volume: 2008
Year: 2008
Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems

Author(s): Vishwanath Natarajan | Rajarajan Senguttuvan | Shreyas Sen | Abhjit Chatterjee
Volume: 2008
Year: 2008
Integrated VCOs for Medical Implant Transceivers

Author(s): Ahmet Tekin | Mehmet R. Yuce | Wentai Liu
Volume: 2008
Year: 2008
Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing

Author(s): E. Simeu | H. N. Nguyen | P. Cauvet | S. Mir | L. Rufer | R. Khereddine
Volume: 2008
Year: 2008
MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing

Author(s): D. C. Keezer | D. Minier | P. Ducharme | D. Viens | G. Flynn | J. McKillop
Volume: 2008
Year: 2008
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator

Author(s): V. Kerzérho | P. Cauvet | S. Bernard | F. Azaïs | M. Renovell | M. Comte | O. Chakib
Volume: 2008
Year: 2008
A Tool for Single-Fault Diagnosis in Linear Analog Circuits with Tolerance Using the T-Vector Approach

Author(s): José A. Soares Augusto | Carlos Beltrán Almeida
Volume: 2008
Year: 2008
Wave Pipelining Using Self Reset Logic

Author(s): Miguel E. Litvin | Samiha Mourad
Volume: 2008
Year: 2008
Delay Efficient 32-Bit Carry-Skip Adder

Author(s): Yu Shen Lin | Damu Radhakrishnan
Volume: 2008
Year: 2008
A Time-Consistent Video Segmentation Algorithm Designed for Real-Time Implementation

Author(s): M. El Hassani | S. Jehan-Besson | L. Brun | M. Revenu | M. Duranton | D. Tschumperlé | D. Rivasseau
Volume: 2008
Year: 2008
Enabling VLSI Processing Blocks for MIMO-OFDM Communications

Author(s): Barbara Cerato | Guido Masera | Emanuele Viterbo
Volume: 2008
Year: 2008
A Programmable Hardware Cellular Automaton: Example of Data Flow Transformation

Author(s): Samuel Charbouillot | Annie Pérez | Daniele Fronte
Volume: 2008
Year: 2008
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

Author(s): Alberto Jiménez-Pacheco | Ángel Fernández-Herrero | Javier Casajús-Quirós
Volume: 2008
Year: 2008
Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

Author(s): Ler Chun Lee | Abu Khari bin A'ain | Albert Victor Kordesch
Volume: 2008
Year: 2008
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers

Author(s): Alpana Agarwal | Chandra Shekhar
Volume: 2008
Year: 2008
Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

Author(s): Paul Bogdan | Tudor Dumitraş | Radu Marculescu
Volume: 2007
Year: 2007
Network Delays and Link Capacities in Application-Specific Wormhole NoCs

Author(s): Zvika Guz | Isask'har Walter | Evgeny Bolotin | Israel Cidon | Ran Ginosar | Avinoam Kolodny
Volume: 2007
Year: 2007
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Author(s): Srinivasan Murali | David Atienza | Luca Benini | Giovanni De Micheli
Volume: 2007
Year: 2007
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Author(s): Andreas Hansson | Kees Goossens | Andrei Rădulescu
Volume: 2007
Year: 2007
Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

Author(s): Andreas Hansson | Kees Goossens | Andrei Rădulescu
Volume: 2007
Year: 2007
Area and Power Modeling for Networks-on-Chip with Layout Awareness

Author(s): Paolo Meloni | Igor Loi | Federico Angiolini | Salvatore Carta | Massimo Barbaro | Luigi Raffo | Luca Benini
Volume: 2007
Year: 2007
Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Author(s): Teijo Lehtonen | Pasi Liljeberg | Juha Plosila
Volume: 2007
Year: 2007
High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

Author(s): Ethiopia Nigussie | Teijo Lehtonen | Sampo Tuuna | Juha Plosila | Jouni Isoaho
Volume: 2007
Year: 2007
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Author(s): Maged Ghoneima | Yehea Ismail | Muhammad Khellah | Vivek De
Volume: 2007
Year: 2007
Low-Power Built-In Self-Test Techniques for Embedded SRAMs

Author(s): Shyue-Kung Lu | Yuang-Cheng Hsiao | Chia-Hsiu Liu | Chun-Lin Yang
Volume: 2007
Year: 2007
Eight-Bit Semiflash A/D Converter

Author(s): D. P. Dimitrov | T. K. Vasileva
Volume: 2007
Year: 2007
On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration

Author(s): P. Guironnet de Massas | P. Amblard | F. Pétrot
Volume: 2007
Year: 2007
Robustness of Transmultiplexed Images

Author(s): Przemysław Sypka | Mariusz Ziółko
Volume: 2007
Year: 2007
Power Consumption and BER of Flip-Flop Inserted Global Interconnect

Author(s): Jingye Xu | Abinash Roy | Masud H. Chowdhury
Volume: 2007
Year: 2007
Advanced Readout System IC Current Mode Semi-Gaussian Shapers Using CCIIs and OTAs

Author(s): Thomas Noulis | Constantinos Deradonis | Stylianos Siskos
Volume: 2007
Year: 2007
Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

Author(s): Jianhong Xiao | Guang Zhang | Tianwei Li | Jose Silva-Martinez
Volume: 2007
Year: 2007
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Author(s): Tooraj Nikoubin | Poona Bahrebar | Sara Pouri | Keivan Navi | Vaez Iravani
Volume: 2010
Year: 2010
CORDIC Architectures: A Survey

Author(s): B. Lakshmi | A. S. Dhar
Volume: 2010
Year: 2010
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

Author(s): Usha S. Mehta | Kankar S. Dasgupta | Niranjan M. Devashrayee
Volume: 2010
Year: 2010
Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Author(s): Saumil G. Merchant | Gregory D. Peterson
Volume: 2010
Year: 2010
A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Author(s): Akila Gothandaraman | Gregory D. Peterson | G. Lee Warren | Robert J. Hinde | Robert J. Harrison
Volume: 2010
Year: 2010
Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

Author(s): JunKyu Lee | Gregory D. Peterson | Robert J. Harrison | Robert J. Hinde
Volume: 2010
Year: 2010
Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance

Author(s): Yao Xu | Ashok Srivastava | Ashwani K. Sharma
Volume: 2010
Year: 2010
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Author(s): Yan Zhu | U-Fat Chio | He-Gong Wei | Sai-Weng Sin | Seng-Pan U | R. P. Martins
Volume: 2010
Year: 2010
Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

Author(s): K. Odame | P. E. Hasler
Volume: 2010
Year: 2010
Error Immune Logic for Low-Power Probabilistic Computing

Author(s): Bo Marr | Jason George | Brian Degnan | David V. Anderson | Paul Hasler
Volume: 2010
Year: 2010
Post-CTS Delay Insertion

Author(s): Jianchao Lu | Baris Taskin
Volume: 2010
Year: 2010
Low-Cost Allocator Implementations for Networks-on-Chip Routers

Author(s): Min Zhang | Chiu-Sing Choy
Volume: 2009
Year: 2009
Reduced Voltage Scaling in Clock Distribution Networks

Author(s): Khader Mohammad | Ayman Dodin | Bao Liu | Sos Agaian
Volume: 2009
Year: 2009
FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

Author(s): K. Selvajyothi | P. A. Janakiraman
Volume: 2010
Year: 2010
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Author(s): Jun Zhao | Yong-Bin Kim
Volume: 2010
Year: 2010
A Multilevel Congestion-Based Global Router

Author(s): Logan Rakai | Laleh Behjat | Shawki Areibi | Tamas Terlaky
Volume: 2009
Year: 2009
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Author(s): Ramesh Vaddi | S. Dasgupta | R. P. Agarwal
Volume: 2009
Year: 2009
Particle Swarm Optimization for Constrained Instruction Scheduling

Author(s): Rehab F. Abdel-Kader
Volume: 2008
Year: 2009
Design and Characterization of the Next Generation Nanowire Amplifiers

Author(s): Sotoudeh Hamedi-Hagh | Ahmet Bindal
Volume: 2008
Year: 2009
CONTANGO: Integrated Optimization of SoC Clock Networks

Author(s): Dong-Jin Lee | Igor L. Markov
Volume: 2011
Year: 2011
Buffer Planning for IP Placement Using Sliced-LFF

Author(s): Ou He | Sheqin Dong | Jinian Bian | Satoshi Goto
Volume: 2011
Year: 2011
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Author(s): Usha Mehta | Kankar Dasgupta | Niranjan Devashrayee
Volume: 2011
Year: 2011
Shedding Physical Synthesis Area Bloat

Author(s): Ying Zhou | Charles J. Alpert | Zhuo Li | Cliff Sze | Louise H. Trevillyan
Volume: 2011
Year: 2011
The Impact of Statistical Leakage Models on Design Yield Estimation

Author(s): Rouwaida Kanj | Rajiv Joshi | Sani Nassif
Volume: 2011
Year: 2011
New Considerations for Spectral Classification of Boolean Switching Functions

Author(s): J. E. Rice | J. C. Muzio | N. Anderson
Volume: 2011
Year: 2011
A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Author(s): Sergio Saponara | Tommaso Baldetti | Luca Fanucci
Volume: 2010
Year: 2010
An Approach for Implementing State Machines with Online Testability

Author(s): P. K. Lala | A. Mathews | J. P. Parkerson
Volume: 2010
Year: 2010
A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor

Author(s): Mohammad Javad Sharifi | Davoud Bahrepour
Volume: 2009
Year: 2009
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

Author(s): Faizal A. Samman | Thomas Hollstein | Manfred Glesner
Volume: 2009
Year: 2009
Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach

Author(s): E. J. Peralías | M. A. Jalón | A. Rueda
Volume: 2008
Year: 2008
A Programmable Max-Log-MAP Turbo Decoder Implementation

Author(s): Perttu Salmela | Harri Sorokin | Jarmo Takala
Volume: 2008
Year: 2008
A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

Author(s): Sreehari Rao Patri | K. S. R. Krishna Prasad
Volume: 2008
Year: 2008
A Pull-in Based Test Mechanism for Device Diagnostic and Process Characterization

Author(s): L. A. Rocha | L. Mol | E. Cretu | R. F. Wolffenbuttel | J. Machado da Silva
Volume: 2008
Year: 2008
Power Considerations in Banked CAMs: A Leakage Reduction Approach

Author(s): Pedro Echeverría | José L. Ayala | Marisa López-Vallejo
Volume: 2008
Year: 2008
An FFT Core for DVB-T/DVB-H Receivers

Author(s): A. Cortés | I. Vélez | I. Zalbide | A. Irizar | J. F. Sevillano
Volume: 2008
Year: 2008
Antirandom Testing: A Distance-Based Approach

Author(s): Shen Hui Wu | Sridhar Jandhyala | Yashwant K. Malaiya | Anura P. Jayasumana
Volume: 2008
Year: 2008
High-Performance Timing-Driven Rank Filter

Author(s): Péter Szántó | Gábor Szedő | Béla Fehér
Volume: 2008
Year: 2008
A Video Specific Instruction Set Architecture for ASIP design

Author(s): Zheng Shen | Hu He | Yanjun Zhang | Yihe Sun
Volume: 2007
Year: 2007
Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

Author(s): Reeba Korah | J.Raja Paul Perinbam
Volume: 2008
Year: 2008
Floorplan-Driven Multivoltage High-Level Synthesis

Author(s): Xianwu Xing | Ching Chuen Jong
Volume: 2009
Year: 2009
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

Author(s): Debasri Saha | Susmita Sur-Kolay
Volume: 2011
Year: 2011
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Author(s): Yoni Aizik | Avinoam Kolodny
Volume: 2011
Year: 2011
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

Author(s): M. A. R. Chaudhry | Z. Asad | A. Sprintson | J. Hu
Volume: 2011
Year: 2011
Selected Papers from the Midwest Symposium on Circuits and Systems

Author(s): Gregory D. Peterson | Ethan Farquhar | Benjamin Blalock
Volume: 2010
Year: 2010
Selected Papers from International Mixed Signals Testing and GHz/Gbps Test Workshop

Author(s): Bozena Kaminska | Marcelo Lubaszewski | José Machado da Silva
Volume: 2008
Year: 2008
International Conference on Electronics, Circuits, and Systems

Author(s): Jean-Baptiste Begueret | Thierry Taris
Volume: 2008
Year: 2008
Networks-on-Chip: Emerging Research Topics and Novel Ideas

Author(s): Davide Bertozzi | Shashi Kumar | Maurizio Palesi
Volume: 2007
Year: 2007
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