Author(s): Deepak Kumar, Ranjan Kumar Behera, K. S. Pandey
Journal: International Journal of Engineering Research
ISSN 2319-6890
Volume: 2;
Issue: 3;
Start page: 225;
Date: 2013;
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Keywords: Supervector processor | Superscalar processor | SUIF | Trimaran | Vector processor.
ABSTRACT
To maximize the available performance is always a goal in microprocessor design. In this paper a new technique has been implemented which exploits the advantage of both superscalar and vector processing technique in a proposed processor called Supervector processor. Vector processor operates on array of data called vector and can greatly improve certain task such as numerical simulation and tasks which requires huge number crunching. On other handsuperscalar processor issues multiple instructions per cyclewhich can enhance the throughput. To implement parallelism multiple vector instructions were issued and executed per cycle in superscalar fashion. Case study has been done on various benchmarks to compare the performance of proposedsupervector processor architecture with superscalar and vectorprocessor architecture. Trimaran Framework has been used in order to evaluate the performance of the proposed supervector processor scheme.
Journal: International Journal of Engineering Research
ISSN 2319-6890
Volume: 2;
Issue: 3;
Start page: 225;
Date: 2013;
VIEW PDF


Keywords: Supervector processor | Superscalar processor | SUIF | Trimaran | Vector processor.
ABSTRACT
To maximize the available performance is always a goal in microprocessor design. In this paper a new technique has been implemented which exploits the advantage of both superscalar and vector processing technique in a proposed processor called Supervector processor. Vector processor operates on array of data called vector and can greatly improve certain task such as numerical simulation and tasks which requires huge number crunching. On other handsuperscalar processor issues multiple instructions per cyclewhich can enhance the throughput. To implement parallelism multiple vector instructions were issued and executed per cycle in superscalar fashion. Case study has been done on various benchmarks to compare the performance of proposedsupervector processor architecture with superscalar and vectorprocessor architecture. Trimaran Framework has been used in order to evaluate the performance of the proposed supervector processor scheme.