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Frequency and Power Estimator for Digital Receivers in Doppler Shift Environments

Author(s): M. Saber, M. T. A. Khan & Y. Jitsumatsu

Journal: Signal Processing : An International Journal
ISSN 1985-2339

Volume: 5;
Issue: 5;
Start page: 185;
Date: 2011;
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Keywords: Digital Phase Locked Loop (DPLL) | Frequency Estimator | FPGA.

A frequency estimator well suited for digital receivers is proposed. Accurate estimates ofunknown frequency and power of input sinusoidal signal, in the presence of additive whiteGaussian noise (AWGN), are provided. The proposed structure solve the problems of traditionalphase locked loop (PLL) such as, narrow tracking range, overshoot, long settle time, doublefrequency ripples in the loop and stability. Proposed method can estimate frequencies up to halfthe sampling frequency irrespective of the input signal power. Furthermore, it provides stabilityand allows fast tracking for any changes in input frequency. The estimator is also implementedusing field programmable gate array (FPGA), consumes 127 mW and works at a frequency of225 MHz. Proposed method can estimate the fluctuation in frequency of transmitter’s oscillator,can be used as a frequency shift keying receiver and can also be applied as a digital receiver inDoppler shift environment.
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