Author(s): Akitoshi Matsuda
Journal: International Journal of Image Processing and Visual Communication
ISSN 2319-1724
Volume: 1;
Issue: 2;
Start page: 29;
Date: 2012;
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Keywords: Hardware | C Source Code | Optimization | Verification | Visualization | Circuit performance
ABSTRACT
Recently, in the development of complex embedded systems, a model-based design approach has attracted considerable attention. We propose a high-level synthesis method involving C-based design that pays attention to efficient development of hardware design in complex embedded systems. By modeling the C source code, the structure is visualized, and this makes it easier for third parties to understand it. In this design flow, if the entire structure can be visualized, the system-level C source code can be optimized, resulting in an improvement in design quality and a shortening of the design cycle. The optimization of system-level C source code is more efficient compared to co-design and co-verification in hardware and software. Therefore, system-level C source code visualization and optimization is proposed to facilitate consistent hardware design in this paper. Experimental results indicate that our technique improves circuit performance by as much as 9.6% and reduces the circuit area by up to 10% in hardware design.
Journal: International Journal of Image Processing and Visual Communication
ISSN 2319-1724
Volume: 1;
Issue: 2;
Start page: 29;
Date: 2012;
VIEW PDF
DOWNLOAD PDF Original pageKeywords: Hardware | C Source Code | Optimization | Verification | Visualization | Circuit performance
ABSTRACT
Recently, in the development of complex embedded systems, a model-based design approach has attracted considerable attention. We propose a high-level synthesis method involving C-based design that pays attention to efficient development of hardware design in complex embedded systems. By modeling the C source code, the structure is visualized, and this makes it easier for third parties to understand it. In this design flow, if the entire structure can be visualized, the system-level C source code can be optimized, resulting in an improvement in design quality and a shortening of the design cycle. The optimization of system-level C source code is more efficient compared to co-design and co-verification in hardware and software. Therefore, system-level C source code visualization and optimization is proposed to facilitate consistent hardware design in this paper. Experimental results indicate that our technique improves circuit performance by as much as 9.6% and reduces the circuit area by up to 10% in hardware design.
