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A High Speed CMOS Parallel Counter Using Pipeline Partitioning

Author(s): K. Thamaraiselvan, C. Gayathri, N.Divya

Journal: International Journal of Engineering Research
ISSN 2319-6890

Volume: 2;
Issue: 8;
Start page: 491;
Date: 2013;
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Keywords: High performance Counter design | Parallel counter design | Pipeline counter design

A high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path) is proposed, and can be implemented using only three simple repeated CMOS-logic module types: an initial module generates anticipated counting states for higher significant bit modules through the state look-ahead path, simple D-type flip-flops, and 2-bit counters. The state look-ahead path prepares the counting path’s next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge. The structure is scalable to arbitrary N-bit counter widths (2-to-2N range) using only the three module types and no fan-in or fan-out increase. The counter’s delay is comprised of the initial module access time (a simple 2-bit counting stage), one three-input AND-gate delay, and a D-type flip-flop setup-hold time. Thus the proposed counter can be implemented without AND gate and hence speed can be increased. The design can be implemented with Modelsim simulator. The parallel counter can give a maximum operating speed of 2GHz for 8-bit counter. Finally, the area of a sample 8-bit counter is 78 125 µm2 (510 transistors) and power consumption is 13.89Mw at 2GHz.
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