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Implementation of AES as a Custom Hardware using NIOS II Processor

Author(s): Meghana Hasamnis | Priyanka Jambhulkar | S.S. Limaye

Journal: Advanced Computing : an International Journal
ISSN 2229-726X

Volume: 3;
Issue: 4;
Start page: 77;
Date: 2012;
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Keywords: Advanced Encryption Standard (AES) | NIOS II Processor | SOPC Builder | NIOS II IDE.

In this paper Advanced Encryption Standard (AES) algorithm has been designed and implemented as custom hardware. The algorithm is controlled through C-code written in NIOS II IDE. AES as a custom hardware is interfaced with the system designed around NIOS II Processor using SOPC builder tool. AES is written in hardware in VHDL language and the interface is through GPIO (General Purpose Input / Output Port). AES implemented using data size of 128 bits, while the length of the key used is of 128 bits. The key size of AES used is of 128 bits, as it is secure from the different attacks in existence. The FPGA used is CYCLONE II from Altera. AES as a custom hardware increases the speed of encryption and serves as an accelerator and hence improves the performance of the system.
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