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A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator

Author(s): Mohamed Saber Saber Elsayes, Yutaka Jitsumatsu, Mohamed tahir Abasi Khan

Journal: Signal Processing : An International Journal
ISSN 1985-2339

Volume: 5;
Issue: 4;
Start page: 142;
Date: 2011;
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Keywords: Digital Phase locked loop (DPLL) | Field Programmable Gate Array (FPGA) | Software Defined Radio (SFDR) | Read Only Memory (ROM) | Spurious Free Dynamic Range (SFDR).

This paper analyzes and designs a second order digital phase-locked loop (DPLL), and presentslow power architecture for DPLL. The proposed architecture reduces the high power consumptionof conventional DPLL, which results from using a read only memory (ROM) in implementation ofthe numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, inwhich no ROM is used. DPLL is designed and implemented using FPGA, consumes 237 mw,which means more than 25% saving in power consumption, and works at faster clock frequencycompared to traditional architecture.
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