Academic Journals Database
Disseminating quality controlled scientific knowledge

Physical IC debug ─ backside approach and nanoscale challenge

ADD TO MY LIST
 
Author(s): C. Boit | R. Schlangen | A. Glowacki | U. Kindereit | T. Kiyan | U. Kerst | T. Lundquist | S. Kasapi | H. Suzuki

Journal: Advances in Radio Science - Kleinheubacher Berichte
ISSN 1684-9965

Volume: 6;
Start page: 265;
Date: 2008;
VIEW PDF   PDF DOWNLOAD PDF   Download PDF Original page

ABSTRACT
Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach.
RPA Switzerland

RPA Switzerland

Robotic process automation

    

Tango Jona
Tangokurs Rapperswil-Jona