Author(s): Abderrazzak El Boukili
Journal: International Journal of Computer Science and Engineering Survey
ISSN 0976-3252
Volume: 4;
Issue: 2;
Start page: 1;
Date: 2013;
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Keywords: Modeling and simulation | thermal effects | 3D integrated circuits | CMOS.
ABSTRACT
Interconnect is one of the main performance determinant of modernintegrated circuits(ICs). The newtechnology of verticalICsplaces circuitblocks in the vertical dimension in addition to the conventionalhorizontal plane.Compared to the planarICs, verticalICshave shorter latencies as well as lower powerconsumption due to shorter wires. This also increasesspeed, improves performancesand adds toICsdensity.The benefitsof vertical ICs increase as we stack more dies, due to successive reductions in wirelengths.However,as we stack more dies, thelatticeself-heating becomesa challengingandcriticalissuedue to the difficulty incooling downthe layers away from the heat sink.In this paper, we provide aquantitativeelectro-thermalanalysis of thetemperature rise due to stacking. Mathematical models basedonsteady statenon-isothermal drift-diffusion transport equations coupled to heat flow equationare used.Thesephysically based models and the different heat sources in semiconductor devices will be presentedand discussed.Three dimensional numerical results did show that, compared to the planarICs, thevertical ICs with 2-dietechnologyincrease the maximum temperature by 17 Kelvinin the dieaway fromthe heat sink.These numerical results willalsobe presented and analyzedfor a typical2-diestructure ofcomplementary metal oxide semiconductor(CMOS)transistors.
Journal: International Journal of Computer Science and Engineering Survey
ISSN 0976-3252
Volume: 4;
Issue: 2;
Start page: 1;
Date: 2013;
VIEW PDF
DOWNLOAD PDF Original pageKeywords: Modeling and simulation | thermal effects | 3D integrated circuits | CMOS.
ABSTRACT
Interconnect is one of the main performance determinant of modernintegrated circuits(ICs). The newtechnology of verticalICsplaces circuitblocks in the vertical dimension in addition to the conventionalhorizontal plane.Compared to the planarICs, verticalICshave shorter latencies as well as lower powerconsumption due to shorter wires. This also increasesspeed, improves performancesand adds toICsdensity.The benefitsof vertical ICs increase as we stack more dies, due to successive reductions in wirelengths.However,as we stack more dies, thelatticeself-heating becomesa challengingandcriticalissuedue to the difficulty incooling downthe layers away from the heat sink.In this paper, we provide aquantitativeelectro-thermalanalysis of thetemperature rise due to stacking. Mathematical models basedonsteady statenon-isothermal drift-diffusion transport equations coupled to heat flow equationare used.Thesephysically based models and the different heat sources in semiconductor devices will be presentedand discussed.Three dimensional numerical results did show that, compared to the planarICs, thevertical ICs with 2-dietechnologyincrease the maximum temperature by 17 Kelvinin the dieaway fromthe heat sink.These numerical results willalsobe presented and analyzedfor a typical2-diestructure ofcomplementary metal oxide semiconductor(CMOS)transistors.
