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Single Precision Floating Point FFT

Author(s): Ujwal S. Ghate

Journal: International Journal of Computer Applications
ISSN 0975-8887

Volume: ncipet;
Issue: 3;
Date: 2012;
Original page

Keywords: IEEE Floating-point | FPGA | FFT | HDL

In this paper the design and implementation of 32 bit IEEE 754 single precision floating point FFT architecture is proposed. Usually for FFT calculation the sequential circuits use for mantissa adjustment which is somewhat tedious job So, new approach is define for calculating FFT in pure combinational circuits form. The simulation result are compare with the quartus II and Active HDL software also it is cross verified with Matlab . The algorithm is implemented on FPGA
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