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International Journal of VLSI Design & Communication Systems

ISSN: 0976--1527
Publisher: Academy & Industry Research Collaboration Center (AIRCC)


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Design of Ultra Low Power 8-Channel Analog Multiplexer Using Dynamic Threshold for Biosignals PDF available

Author(s): D.Hari Priya | V. Rajesh | P. Rama Krishna | K. S. Rao
Volume: 4
Issue: 5
Year: 2013
A New Improved MCML Logic for DPA Resistant Circuits PDF available

Author(s): A.K.Tripathy | A.Prathiba | V.S.Kanchana Bhaaskaran
Volume: 4
Issue: 5
Year: 2013
Low Power Reduced Instruction Set Architecture Using Clock Gating Technique PDF available

Author(s): M.Kamaraju | G.Chinavenkateswararao
Volume: 4
Issue: 5
Year: 2013
Design and Implementation of Complex Floating Point Processor Using FPGA PDF available

Author(s): Murali Krishna Pavuluri | T.S.R. Krishna Prasad | Ch.Rambabu
Volume: 4
Issue: 5
Year: 2013
A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier PDF available

Author(s): Shridhar R. Sahu | A. Y. Deshmukh
Volume: 4
Issue: 5
Year: 2013
Low Cost Reversible Signed Comparator PDF available

Author(s): Farah Sharmin | Rashida Hasan | Rajib Kumar Mitra | Anisur Rahman
Volume: 4
Issue: 5
Year: 2013
Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits PDF available

Author(s): K.Srilakshmi | Y.Syamala | A.Suvir Vikram
Volume: 4
Issue: 5
Year: 2013
An Integrated-Approach for Designing and Testing Specific Processors PDF available

Author(s): Cesar Giacomini Penteado | Sérgio Takeo Kofuji | Edward David Moreno
Volume: 4
Issue: 5
Year: 2013
Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI) Technique PDF available

Author(s): Y. Syamala | K. Srilakshmi | N. Somasekhar Varma
Volume: 4
Issue: 5
Year: 2013
A New Low Voltage P-MOS Bulk Driven Current Mirror Circuit PDF available

Author(s): Anuj Dugaya | Laxmi Kumre
Volume: 4
Issue: 4
Year: 2013
Analog Modeling of Recursive Estimator Design with Filter Design Model PDF available

Author(s): R.Rajendra prasad | M.V.Subramanyam | K.Satya Prasad
Volume: 4
Issue: 4
Year: 2013
Design of High Efficiency Two Stage Power Amplifier in 0.13µM RF CMOS Technology for 2.4GHZ WLAN Application PDF available

Author(s): Shridhar R. Sahu | A.Y. Deshmukh
Volume: 4
Issue: 4
Year: 2013
Performance Analysis of Modified QSERL Circuit PDF available

Author(s): Shipra Upadhyay | R.A. Mishra | R. K. Nagaria
Volume: 4
Issue: 4
Year: 2013
Extended K-Map for Minimizing Multiple Output Logic Circuits PDF available

Author(s): Palash Das | Bikromadittya Mondal
Volume: 4
Issue: 4
Year: 2013
Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso Platform PDF available

Author(s): Karthik Reddy. G
Volume: 4
Issue: 4
Year: 2013
Reduction of Bus Transition for Compressed Code Systems PDF available

Author(s): S. R. Malathi | R. Ramya Asmi
Volume: 4
Issue: 1
Year: 2013
Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data PDF available

Author(s): Sunita M.S | Kanchana Bhaaskaran V.S
Volume: 4
Issue: 1
Year: 2013
A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology PDF available

Author(s): Tarun Kr. Gupta | Kavita Khare
Volume: 4
Issue: 1
Year: 2013
A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric PDF available

Author(s): Anil Yadav | Gayatri Mehta | Alex K. Jones | Justin Stander
Volume: 4
Issue: 1
Year: 2013
A Multi-Objective Perspective for Operator Scheduling Using Finegrained DVS Architectures PDF available

Author(s): Rajdeep Mukherjee | Priyankar Ghosh | Pallab Dasgupta | Ajit Pal
Volume: 4
Issue: 1
Year: 2013
Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data PDF available

Author(s): Vaishali Dhare | Usha Mehta
Volume: 4
Issue: 1
Year: 2013
Ternary Tree Asynchronous Interconnect Network for GALS' SOC PDF available

Author(s): Vivek E. Khetade | S.S. Limaye
Volume: 4
Issue: 1
Year: 2013
Realization of Transmitter and Receiver Architecture for Downlink Channels in 3-GPP LTE PDF available

Author(s): S. Syed Ameer Abbas | J. Rahumath Nisha | M. Beril Sahaya Mary | S. J. Thiruvengadam
Volume: 4
Issue: 1
Year: 2013
Dual Field Dual Core Secure Cryptoprocessor on FPGA Platform PDF available

Author(s): C. Veeraraghavan | K. Rajendran
Volume: 4
Issue: 1
Year: 2013
An Efficient CNTFET Based 7-Input Minority Gate PDF available

Author(s): Samira Shirinabadi Farahani | Ronak Zarhoun | Mohammad Hossein Moaiyeri | Keivan Navi
Volume: 4
Issue: 1
Year: 2013
Performance Evaluation of Throughput Maximization in MC-CDMA for 4G Standard PDF available

Author(s): Hema Kale | C.G. Dethe | M.M. Mushrif
Volume: 3
Issue: 6
Year: 2013
Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates PDF available

Author(s): H R Bhagyalakshmi | M K Venkatesha
Volume: 3
Issue: 6
Year: 2013
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture PDF available

Author(s): Hanie Ghaedrahmat | Khosrow Hajsadeghi
Volume: 3
Issue: 6
Year: 2013
Synthesis Optimization for Finite State Machine Design in FPGAs PDF available

Author(s): R.Uma | P.Dhavachelvan
Volume: 3
Issue: 6
Year: 2013
Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology PDF available

Author(s): Joyashree Bag | Rajanna K M | Subir Kumar Sarkar
Volume: 3
Issue: 6
Year: 2013
Design of Reversible Multipliers for Linear Filtering Applications in DSP PDF available

Author(s): Rakshith Saligram | Rakshith T.R
Volume: 3
Issue: 6
Year: 2013
Low Power Dynamic Buffer Circuits PDF available

Author(s): Amit Kumar Pandey | Ram Awadh Mishra | Rajendra Kumar Nagaria
Volume: 3
Issue: 5
Year: 2012
Modeling of Built-In Potential Variations of Cylindrical Surrounding Gate (CSG) MOSFETs PDF available

Author(s): Santosh Kumar Gupta | S.Baishya
Volume: 3
Issue: 5
Year: 2012
Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM PDF available

Author(s): Prathima. A | Kiran Bailey | K.S.Gurumurthy
Volume: 3
Issue: 5
Year: 2012
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme PDF available

Author(s): Majed ValadBeigi | Farshad Safaei | Bahareh Pourshirazi
Volume: 3
Issue: 5
Year: 2012
Design & Analysis of A Charge Re-Cycle Based Novel Lphs Adiabatic Logic Circuits for Low Power Applications PDF available

Author(s): Sanjeev Rai | Ram Awadh Mishra | Govind Krishna Pal | Sudarshan Tiwari
Volume: 3
Issue: 5
Year: 2012
Modified March C-With Concurrency in Testing for Embedded Memory Applications PDF available

Author(s): Muddapu Parvathi | N.Vasantha | K.Satya Parasad
Volume: 3
Issue: 5
Year: 2012
Design and Implementation of Analog Multiplier with Improved Linearity PDF available

Author(s): Nandini A.S | Sowmya Madhavan | Chirag Sharma
Volume: 3
Issue: 5
Year: 2012
A XOR Threshold Logic Implementation Through Resonant Tunneling Diode PDF available

Author(s): Nitesh Kumar Dixit | Vinod Kumari
Volume: 3
Issue: 5
Year: 2012
Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System PDF available

Author(s): Chaitali Biswas Dutta | Partha Garai | Amitabha Sinha
Volume: 3
Issue: 5
Year: 2012
An Efficient Approach for Four-Layer Channel Routing in VLSI Design PDF available

Author(s): Ajoy Kumar Khan | Bhaskar Das | Tapas Kumar Bayen
Volume: 3
Issue: 5
Year: 2012
Quaternary Logic and Applications Using Multiple Quantum Well Based SWSFETs PDF available

Author(s): P. Gogna | M. Lingalugari | J.Chandy | F.Jain | E.Heller | E-S.Hasaneen
Volume: 3
Issue: 5
Year: 2012
High Fin Width Mosfet Using Gaa Structure PDF available

Author(s): S.L.Tripathi | Ramanuj Mishra | R.A.Mishra
Volume: 3
Issue: 5
Year: 2012
Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design PDF available

Author(s): Kiran Agarwal Gupta | Dinesh K Anvekar | Venkateswarlu V
Volume: 3
Issue: 5
Year: 2012
Improved Extended XY On-Chip Routing in Diametrical 2D MEsh NOC PDF available

Author(s): Prasun Ghosal | Tuhin Subhra Das
Volume: 3
Issue: 5
Year: 2012
Design of Low Power Sigma Delta ADC PDF available

Author(s): Mohammed Arifuddin Sohel | K. Chenna Kesava Reddy | Syed Abdul Sattar
Volume: 3
Issue: 4
Year: 2012
FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme PDF available

Author(s): Durga Sowjanya | K N H Srinivas | P Venkata Ganapathi
Volume: 3
Issue: 4
Year: 2012

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