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VLSI Design

ISSN: 1065--514X
Publisher: Hindawi Publishing Corporation


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Advancements in Power Supply Current Testing

Author(s): Rafic Z. Makki
Volume: 5
Issue: 3
Year: 1997
Application of Dynamic Supply Current Monitoring toTesting Mixed-Signal Circuits

Author(s): Mahmoud A. Al-Qutayri | Peter R. Shepherd
Volume: 5
Issue: 3
Year: 1997
Current Testing of CMOS Combinational Circuits withSingle Floating Gate Defects

Author(s): Victor H. Champac | Joan Figueras
Volume: 5
Issue: 3
Year: 1997
IDDQ Testing Experiments for Various CMOS LogicDesign Structures

Author(s): A. Toukmaji | R. Helms | R. Makki | W. Mikhail | R. Toole
Volume: 5
Issue: 3
Year: 1997
IDDQ Detectable Bridges in Combinational CMOS Circuits

Author(s): E. Isern | J. Figueras
Volume: 5
Issue: 3
Year: 1997
Layout Modeling and Design Space Exploration in Pss1 System

Author(s): Fur-Shing Tsai | Yu-Chin Hsu
Volume: 5
Issue: 2
Year: 1997
Module Selection in Microarchitectural Synthesis forMultiple Critical Constraint Satisfaction

Author(s): Ian G. Harris | Alex Orailo─člu
Volume: 5
Issue: 2
Year: 1997
Linking Behavioral, Structural, and Physical Modelsof Hardware

Author(s): Fadi J. Kurdahi
Volume: 5
Issue: 2
Year: 1997
Combining Technology Mapping With Layout

Author(s): Massoud Pedram | Narasimha Bhat | Ernest S. Kuh
Volume: 5
Issue: 2
Year: 1997
Taking Thermal Considerations Into Account DuringHigh-Level Synthesis

Author(s): Jen-Pin Weng | Alice C. Parker
Volume: 5
Issue: 2
Year: 1997
Effective Coupling Between Logic Synthesis and LayoutTools for Synthesis of Area and Speed-Efficient Circuits

Author(s): Mandalagiri S. Chandrasekhar | Robert H. McCharles | David E. Wallace
Volume: 5
Issue: 2
Year: 1997
Statistical Module Level Area and Delay Estimation

Author(s): Akhilesh Tyagi
Volume: 5
Issue: 2
Year: 1997
Datapath Optimization Using Layout Information: An Empirical Study

Author(s): Allen C.-H. Wu
Volume: 5
Issue: 2
Year: 1997
RT Component Sets for High-Level Design Applications

Author(s): Nikil D. Dutt | Pradip K. Jha
Volume: 5
Issue: 2
Year: 1997
High-Level Graphical Abstraction in Digital Design

Author(s): Murray W. Pearson | Paul J. Lyons | Mark D. Apperley
Volume: 5
Issue: 1
Year: 1996
A New Theory for Testability-Preserving Optimization ofCombinational Circuits

Author(s): Jiabi Zhu | Mostafa Abd-El-Barr | Carl McCrosky
Volume: 5
Issue: 1
Year: 1996
Zener Zap Anti-Fuse Trim in VLSI Circuits

Author(s): Donald T. Comer
Volume: 5
Issue: 1
Year: 1996
An Efficient and Fast Algorithm for RoutingOver the Cells

Author(s): Kuo-En Chang | Sei-Wang Chen
Volume: 5
Issue: 1
Year: 1996
A Greedy Algorithm for Over-The-Cell Channel Routing

Author(s): Gudni Gudmundsson | Simeon Ntafos
Volume: 5
Issue: 1
Year: 1996
Greedy Segmented Channel Router

Author(s): Dinesh Bhatia | V. Shankar
Volume: 5
Issue: 1
Year: 1996
TOGAPS: A Testability Oriented GeneticAlgorithm For Pipeline Synthesis

Author(s): C. P. Ravikumar | V. Saxena
Volume: 5
Issue: 1
Year: 1996
Improving Path Sensitizability ofCombinational Circuits

Author(s): Bhanu Kapoor | V. S. S. Nair
Volume: 5
Issue: 1
Year: 1996
DP-FPGA: An FPGA Architecture Optimized for Datapaths

Author(s): Don Cherepacha | David Lewis
Volume: 4
Issue: 4
Year: 1996
A Sea-of-Gates Style FPGA Placement Algorithm

Author(s): Kalapi Roy | Bingzhong (David) Guan | Carl Sechen
Volume: 4
Issue: 4
Year: 1996
A Timing-Driven Partitioning System for Multiple FPGAs

Author(s): Kalapi Roy | Carl Sechen
Volume: 4
Issue: 4
Year: 1996
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Author(s): Stephen Brown | Muhammad Khellah | Guy Lemieux
Volume: 4
Issue: 4
Year: 1996
Field-Programmable Gate Arrays

Author(s): Dinesh Bhatia
Volume: 4
Issue: 4
Year: 1996
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Author(s): Srilata Raman | C. L. Liu | Larry G. Jones
Volume: 4
Issue: 4
Year: 1996
Erratum

Volume: 4
Issue: 3
Year: 1996
A Novel Path Delay Fault Simulator Using Binary Logic

Author(s): Ananta K. Majhi | James Jacob | Lalit M. Patnaik
Volume: 4
Issue: 3
Year: 1996
Fault Modeling of ECL for High Fault Coverage of Physical Defects

Author(s): Sankaran M. Menon | Yashwant K. Malaiya | Anura P. Jayasumana
Volume: 4
Issue: 3
Year: 1996
PGEN: A Novel Approach to Sequential Circuit Test Generation

Author(s): Wen-Ben Jone | Nigam Shah | Anita Gleason | Sunil R. Das
Volume: 4
Issue: 3
Year: 1996
A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

Author(s): S. Bandyopadhyay | A. Sengupta | B. B. Bhattacharya
Volume: 4
Issue: 3
Year: 1996
Guest Editorial

Author(s): Sunil R. Das
Volume: 4
Issue: 3
Year: 1996
Switch-level Differential Fault Simulation of MOS VLSI Circuits

Author(s): Evstratios Vandris | Gerald Sobelman
Volume: 4
Issue: 3
Year: 1996
Closed Form Aliasing Probability For Q-ary Symmetric Errors

Author(s): Geetani Edirisooriya
Volume: 4
Issue: 3
Year: 1996
A Modified Approach to Test Plan Generation for Combinational Logic Blocks

Author(s): Anupam Basu | Dilip K. Banerji | Amit Basu | T. C. Wilson | Jay C. Majithia
Volume: 4
Issue: 3
Year: 1996
On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

Author(s): M. Srinivas | L. M. Patnaik
Volume: 4
Issue: 3
Year: 1996
HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Author(s): Kyuchull Kim | Kewal K. Saluja
Volume: 4
Issue: 3
Year: 1996
An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations

Author(s): Ausif Mahmood | William I. Baker
Volume: 4
Issue: 2
Year: 1996
An Integrated Hardware Array for Very High Speed Logic Simulation

Author(s): E. Scott Fehr | Stephen A. Szygenda | Granville E. Ott
Volume: 4
Issue: 2
Year: 1996
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

Author(s): Sungho Kang | Youngmin Hur | Stephen A. Szygenda
Volume: 4
Issue: 2
Year: 1996
Hardware Accelerators for VLSI Design

Author(s): Ausif Mahmood
Volume: 4
Issue: 2
Year: 1996
The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Author(s): Neil J. Howard | Andrew M. Tyrrell | Nigel M. Allinson
Volume: 4
Issue: 2
Year: 1996
Hardware Design Rule Checker Using a CAM Architecture

Author(s): Seokjin Kim | Ramalingam Sridhar
Volume: 4
Issue: 2
Year: 1996
A Multi-Terminal Net Router for Field-Programmable Gate Arrays

Author(s): Dinesh Bhatia | Amit Chowdhary
Volume: 4
Issue: 1
Year: 1996
Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

Author(s): B. Majumdar | V. V. Ramakrishna | P. S. Dey | A. K. Majumdar
Volume: 4
Issue: 1
Year: 1996
Design and Implementation of a Low Power Ternary Full Adder

Author(s): A. Srivastava | K. Venkatapathy
Volume: 4
Issue: 1
Year: 1996
Nearly Balanced Quad List Quad Tree -A Data Structure for VLSI Layout Systems

Author(s): Pei-Yung Hsiao
Volume: 4
Issue: 1
Year: 1996
RPA Switzerland

Robotic Process Automation Switzerland

    

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